startup.s

支持三星原产的S3C2413开发板

BringUpWinCE
	
	ldr	 r0, = GPFDAT
	mov	 r1, #0xf0
	str	 r1, [r0]

		[ {TRUE}		
	; Clear RAM.
	;
	mov 	r1,#0
	mov 	r2,#0
	mov 	r3,#0
	mov 	r4,#0
	mov 	r5,#0
	mov 	r6,#0
	mov 	r7,#0
	mov 	r8,#0
	
	ldr		r0,=0x30100000   ; Start address (physical 0x3000.0000).
	ldr		r9,=0x03F00000   ; 64MB of RAM.
20	
	stmia	r0!, {r1-r8}
	subs	r9, r9, #32 
	bne		%B20
	]

;------------------------------------------------------------------------------
;   Copy boot loader to memory

	ands	r9, pc, #0xFF000000	; see if we are in flash or in ram
	bne	 %f20			; go ahead if we are already in ram

	; This is the loop that perform copying.
	ldr	 r0, = 0x38000	   ; offset into the RAM 
	add	 r0, r0, #PHYBASE	; add physical base
	mov	 r1, r0		  ; (r1) copy destination
	ldr	 r2, =0x0		; (r2) flash started at physical address 0
	ldr	 r3, =0x10000		; counter (0x40000/4)
10	ldr	 r4, [r2], #4
	str	 r4, [r1], #4
	subs	r3, r3, #1
	bne	 %b10

	; Restart from the RAM position after copying.
	mov pc, r0
	nop
	nop
	nop

	; Shouldn't get here.
	b	   .

	INCLUDE oemaddrtab_cfg.inc
 

	; Compute physical address of the OEMAddressTable.
20	  add	 r11, pc, #g_oalAddressTable - (. + 8)
	ldr	 r10, =PTs		; (r10) = 1st level page table


	; Setup 1st level page table (using section descriptor)	 
	; Fill in first level page table entries to create "un-mapped" regions
	; from the contents of the MemoryMap array.
	;
	;   (r10) = 1st level page table
	;   (r11) = ptr to MemoryMap array

	add	 r10, r10, #0x2000	   ; (r10) = ptr to 1st PTE for "unmapped space"
	mov	 r0, #0x0E		   ; (r0) = PTE for 0: 1MB cachable bufferable
	orr	 r0, r0, #0x400	  ; set kernel r/w permission
25	  mov	 r1, r11		 ; (r1) = ptr to MemoryMap array

	
30	  ldr	 r2, [r1], #4		; (r2) = virtual address to map Bank at
	ldr	 r3, [r1], #4		; (r3) = physical address to map from
	ldr	 r4, [r1], #4		; (r4) = num MB to map

	cmp	 r4, #0		  ; End of table?
	beq	 %f40

	ldr	 r5, =0x1FF00000
	and	 r2, r2, r5		  ; VA needs 512MB, 1MB aligned.		

	ldr	 r5, =0xFFF00000
	and	 r3, r3, r5		  ; PA needs 4GB, 1MB aligned.

	add	 r2, r10, r2, LSR #18
	add	 r0, r0, r3		  ; (r0) = PTE for next physical page

35	  str	 r0, [r2], #4
	add	 r0, r0, #0x00100000	 ; (r0) = PTE for next physical page
	sub	 r4, r4, #1		  ; Decrement number of MB left 
	cmp	 r4, #0
	bne	 %b35			; Map next MB

	bic	 r0, r0, #0xF0000000	 ; Clear Section Base Address Field
	bic	 r0, r0, #0x0FF00000	 ; Clear Section Base Address Field
	b	   %b30			; Get next element
	
40	  tst	 r0, #8
	bic	 r0, r0, #0x0C	   ; clear cachable & bufferable bits in PTE
	add	 r10, r10, #0x0800	   ; (r10) = ptr to 1st PTE for "unmapped uncached space"
	bne	 %b25			; go setup PTEs for uncached space
	sub	 r10, r10, #0x3000	   ; (r10) = restore address of 1st level page table

	; Setup mmu to map (VA == 0) to (PA == 0x30000000).
	ldr	 r0, =PTs		; PTE entry for VA = 0
	ldr	 r1, =0x30000402	 ; uncache/unbuffer/rw, PA base == 0x30000000
	str	 r1, [r0]

	; uncached area.
	add	 r0, r0, #0x0800	 ; PTE entry for VA = 0x0200.0000 , uncached	 
	ldr	 r1, =0x30000402	 ; uncache/unbuffer/rw, base == 0x30000000
	str	 r1, [r0]
	
	; Comment:
	; The following loop is to direct map RAM VA == PA. i.e. 
	;   VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2400
	; Fill in 8 entries to have a direct mapping for DRAM
	;
	ldr	 r10, =PTs		   ; restore address of 1st level page table
	ldr	 r0,  =PHYBASE

	add	 r10, r10, #(0x3000 / 4) ; (r10) = ptr to 1st PTE for 0x30000000

	add	 r0, r0, #0x1E	   ; 1MB cachable bufferable
	orr	 r0, r0, #0x400	  ; set kernel r/w permission
	mov	 r1, #0 
	mov	 r3, #64
45	  mov	 r2, r1		  ; (r2) = virtual address to map Bank at
	cmp	 r2, #0x20000000:SHR:BANK_SHIFT
	add	 r2, r10, r2, LSL #BANK_SHIFT-18
	strlo   r0, [r2]
	add	 r0, r0, #0x00100000	 ; (r0) = PTE for next physical page
	subs	r3, r3, #1
	add	 r1, r1, #1
	bgt	 %b45

	ldr	 r10, =PTs		   ; (r10) = restore address of 1st level page table

	; The page tables and exception vectors are setup.
	; Initialize the MMU and turn it on.
	mov	 r1, #1
	mcr	 p15, 0, r1, c3, c0, 0   ; setup access to domain 0
	mcr	 p15, 0, r10, c2, c0, 0

	mcr	 p15, 0, r0, c8, c7, 0   ; flush I+D TLBs
	mov	 r1, #0x0071		 ; Enable: MMU
	orr	 r1, r1, #0x0004	 ; Enable the cache

	ldr	 r0, =VirtualStart

	cmp	 r0, #0		  ; make sure no stall on "mov pc,r0" below
	mcr	 p15, 0, r1, c1, c0, 0
	mov	 pc, r0		  ;  & jump to new virtual address
	nop

	; MMU & caches now enabled.
	;   (r10) = physcial address of 1st level page table
	;

VirtualStart

	mov	 sp, #0x80000000	; have to be modefied. refer oemaddrtab_cfg.inc, DonGo
	add	 sp, sp, #0x30000	; arbitrary initial super-page stack pointer


	;bl	vloop_led

	VLED_ON		~0x0		; Set for Led value 1 to inform End of Startup status.
	b	   main




;---------------------------------------------------------------------------------------------------
; memoy init function.
				

	LTORG
	
InitMEM		

	;Set SDR Memory parameter control registers
	;adr		r0, =MEMDATA
	add	 r0, pc, #MEMDATA - (. + 8)

	ldr		r1,=BANKCFG	;
	add		r2, r0, #16	;End address of MEMDATA
110
	ldr		r3, [r0], #4
	str		r3, [r1], #4
	cmp		r2, r0
	bne		%B110


	ldr		r2,=BANKCON1
	ldr		r1,[r2]
	bic		r1,r1,#(0x3<<0)
	orr		r1,r1,#(0x1<<0)			;	4nd	:	Issue a PALL command
	str		r1,[r2]			

	ldr		r4,=REFRESH			;	5fh : refresh cycle every 255-clock cycles
	ldr		r0,=0xff
	str		r0,[r4]	

	IF :DEF: mMDR
	ldr		r4,=DSC1			;   for MDRAM hsjang 0605017
	ldr		r1,[r4]
	ldr		r0,=0x30000
	orr		r1,r1,r0
	str		r1,[r4]
	ENDIF
	
	mov	r0, #0x100					;	6th : wait 2 auto - clk
120				subs	r0, r0,#1;
	bne	%B120	

	bic		r1,r1,#(0x3<<0)			;	7th	:	Issue a MRS command
	orr		r1,r1,#(0x2<<0)
	str		r1,[r2]			

	ldr		r4,=REFRESH			;	8fh : refresh  normal
	ldr		r0,=REFCYC
	str		r0,[r4]					

	orr		r1,r1,#(0x3<<0)			;	9th	:	Issue a EMRS command
	str		r1,[r2]			

	bic		r1,r1,#(0x3<<0)			;	10th	:	Issue a Normal mode
	str		r1,[r2]			

	mov	pc, lr
	

InitSSMC

	;Set SSMC Memory parameter control registers : AMD Flash
	ldr		r0,=SMBIDCYR0
	ldr		r1,=IDCY0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTRDR0
	ldr		r1,=WSTRD0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTWRR0
	ldr		r1,=WSTWR0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTOENR0
	ldr		r1,=WSTOEN0
	str		r1,[r0]
	
	ldr		r0,=SMBWSTWENR0
	ldr		r1,=WSTWEN0
	str		r1,[r0]
	
	ldr		r0,=SMBCR0
	ldr		r1,=(SMBCR0_2+SMBCR0_1+SMBCR0_0)
	str		r1,[r0]
	
	ldr		r0,=SMBWSTBRDR0
	ldr		r1,=WSTBRD0
	str		r1,[r0]

	
	ldr		r0,=SMBWSTBRDR0
	ldr		r1,=WSTBRD0
	str		r1,[r0]

	ldr		r0,=SSMCCR
	ldr		r1,=((MemClkRatio<<1)+(SMClockEn<<0))
	str		r1,[r0]

;	ldr		r0,=SMBWSTRDR5
;	ldr		r1,=0xe
	str		r1,[r0]
	
	mov pc, lr

MEMDATA		DATA
				DCD		((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<2)+(BW<<0))
				DCD		((BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4) + (1<<28) + (1<<26))
				DCD		((tRAS<<20)+(tRC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
				DCD		((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))


	LTORG
;-------------------------------------------
; Delay routine.

DELAY_100
	
11	
	mov	r10, #100
	
10	subs		r10,r10,#0x1
	bne		%B10

	subs	r11, r11, #0x1
	bne	%B11

	mov	pc, lr

;-------------------------------------------
; Led display(Infinite) .
	
loop_led

	LED_ON	0x3

	ldr r0,=0x800000
10	subs r0, r0, #1
	bne %B10	

	LED_ON	0xC

	ldr r0,=0x800000
12	subs r0, r0, #1
	bne %B12	

	b loop_led

vloop_led

	VLED_ON	0xe

	ldr r0,=0x80000
10	subs r0, r0, #1
	bne %B10	

	VLED_ON	0xf

	ldr r0,=0x80000
12	subs r0, r0, #1
	bne %B12	

	b vloop_led	; Infinite loop






	ENTRY_END

	LEAF_ENTRY MemClear

;       1. Push SVC state onto our stack
	stmdb   sp!, {r4-r8}                   

	; Clear RAM.
	;
	mov 	r1,#0
	mov 	r2,#0
	mov 	r3,#0
	mov 	r4,#0
	mov 	r5,#0
	mov 	r6,#0
	mov 	r7,#0
	mov 	r8,#0
	
	ldr		r0,=0x30780000   ; Start address (physical 0x3000.0000).
	ldr		r9,=0x03880000   ; 64MB of RAM.
20	
	stmia	r0!, {r1-r8}
	subs	r9, r9, #32 
	bne		%B20

	ldmia   sp!, {r4-r8}
	mov     pc, lr                


	END

;-------------------------------------------------------------------------------