decoder.c

skyeye 仿真软件

		case JAL:
    		{
			// Jump And Link
			mstate->gpr[31] = mstate->pc + 8;
			VA msb = clear_bits(mstate->pc + 4, 27, 0);
			mstate->branch_target = msb | (target(instr) << 2);
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}
			return branch_delay;
    		}
    		case BEQ:
    		{
			// Branch On Equal
			if (mstate->gpr[rs(instr)] == mstate->gpr[rt(instr)]) {
				VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
    		case BNE:
    		{
			// Branch On Not Equal
			if (mstate->gpr[rs(instr)] != mstate->gpr[rt(instr)]) {
				VA off = sign_extend_UInt32(offset(instr), 16);
	   			 mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}
	
			return branch_delay;
    		}
    		case BLEZ:
    		{
			// Branch On Less Than Or Equal To Zero
			Int32 x = mstate->gpr[rs(instr)];
			if (x <= 0) {
			    	VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
				mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
		case BGTZ:
    		{
			// Branch On Greater Than Zero
			Int32 x = mstate->gpr[rs(instr)];
			if (x > 0) {
			    	VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
    		case ADDI:
    		{
			// Add Immediate
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 y = sign_extend_UInt32(immediate(instr), 16);
			UInt32 z = x + y;
			// Overflow occurs is sign(x) == sign(y) != sign(z).
			if (bit(x ^ y, 31) == 0 && bit(x ^ z, 31) != 0)
			    	process_integer_overflow(mstate);
			mstate->gpr[rt(instr)] = z;
			return nothing_special;
    		}
		case ADDIU:
    		{
			// Add Immediate Unsigned
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 y = sign_extend_UInt32(immediate(instr), 16);
			UInt32 z = x + y;
			mstate->gpr[rt(instr)] = z;
		
			return nothing_special;
    		}
		case SLTI:
    		{
			// Set On Less Than Immediate
			Int32 x = mstate->gpr[rs(instr)];
			Int32 y = sign_extend_UInt32(immediate(instr), 16);
			mstate->gpr[rt(instr)] = (x < y);
	
			return nothing_special;
    		}
	    	case SLTIU:
    		{
			// Set On Less Than Immediate Unsigned
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 y = sign_extend_UInt32(immediate(instr), 16);
			mstate->gpr[rt(instr)] = (x < y);

			return nothing_special;
    		}
	    	case ANDI:
    		{
			// And Immediate
			UInt16 x = mstate->gpr[rs(instr)];
			UInt16 imm = zero_extend(immediate(instr), 16);
			mstate->gpr[rt(instr)] = x & imm; //Shi yang 2006-08-31
			return nothing_special;
    		}
	    	case ORI:
    		{
			// Or Immediate
			UInt32 x = mstate->gpr[rs(instr)]; //Shi yang 2006-08-09
			UInt16 imm = immediate(instr);
			mstate->gpr[rt(instr)] = x | imm;

			return nothing_special;
    		}
	    	case XORI:
    		{
			// Exclusive Or Immediate
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 imm = immediate(instr);
			mstate->gpr[rt(instr)] = x ^ imm;

			return nothing_special;
    		}
    		case LUI:
    		{
			// Load Upper Immediate
			UInt32 imm = immediate(instr);
			imm <<= 16;
			mstate->gpr[rt(instr)] = imm;

			return nothing_special;
    		}
	    	case COP0:
    		{
			// Coprocessor 0 Operation
			return decode_cop0(mstate, instr);
    		}
	    	case COP1:
    		{
			return decode_cop1(mstate, instr);
			// Coprocessor 1 Operation
			//process_reserved_instruction(mstate);
    		}
		case COP2:
    		{
			// Coprocessor 2 Operation
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case PREF:
		{
			//fprintf(stderr, "PREF instruction,pc=0x%x\n",mstate->pc);
			return nothing_special;
		}
	    	case BEQL:
    		{
			// Branch On Equal Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BNEL:
    		{
			// Branch On Not Equal Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BLEZL:
    		{
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BGTZL:
    		{
			// Branch On Greater Than Zero Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case DADDI:
    		{
			// Doubleword Add Immediate
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case DADDIU:
    		{
			// Doubleword Add Immediate Unsigned
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDL:
    		{
			// Load Doubleword Left
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDR:
    		{
			// Load Doubleword Right
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case SPECIAL2:
		{
			
                        switch (function(instr)) {
				case MADD:
				{
					UInt64 temp1 = mstate->hi << 32 + mstate->lo;
					UInt64 temp2 = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)] + temp1;
					mstate->hi = (temp2 >> 32) & (~0x0);
					mstate->lo = temp2 & (~0x0);
					return nothing_special;
				}	
                                case FMUL:
                                {
                                        mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)];
                                        return nothing_special;
                                }
				case CVT_S://CLZ:
				{
					int i = 31;
					for(i; i >= 0;i--)
						if( mstate->gpr[rs(instr)] & (1 << i))
							break;
						else
							continue;
					 mstate->gpr[rd(instr)] = 31 - i;
                                        return nothing_special;
				}
				default:
		                        // Load Doubleword Right
                		        process_reserved_instruction(mstate);
		                        return nothing_special;
			}
                }

	
		case LB:
    		{
			// Load Byte
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate, va, data_load); //Shi yang 2006-08-10, defined in tlb.c
			UInt32 x; 
			UInt32 y = 0;
			load(mstate, va, pa, &y, 1);
			
			x = sign_extend_UInt32(y & (0xff), 8); //Shi yang 2006-08-10, Sign extend

			mstate->gpr[rt(instr)] = x;

			return nothing_special;
    		}
    		case LH:
    		{
			// Load Halfword
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];

			if (bit(va, 0)) //Check alignment
				process_address_error(data_load, va);
			PA pa = translate_vaddr(mstate,va, data_load); //Shi yang 2006-08-10
			UInt32 x; 
			UInt32 y = 0;
			load(mstate, va, pa, &y, 2);
			x = sign_extend_UInt32(y & (0xffff), 16); //Shi yang 2006-08-10, Sign extend

			mstate->gpr[rt(instr)] = x;
			return nothing_special;
    		}
    		case LWL:
    		{
			// Load Word Left
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate, va, data_load); //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);

			UInt32 reg = mstate->gpr[rt(instr)];

			int syscmd = bits(va, 1, 0);
			if (!big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);

			reg = copy_bits(reg, mem, 31, syscmd * 8);
			mstate->gpr[rt(instr)] = reg;

			return nothing_special;
    		}
    		case LW:
    		{
			// Load Word
			if (mstate->sync_bit)
  			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bits(va, 1, 0)) //Check alignment
				process_address_error(mstate,data_load, va);
			PA pa = translate_vaddr(mstate, va, data_load); //Shi yang 2006-08-10
			UInt32 x;
			UInt32 y = 0;
			load(mstate, va, pa, &y, 4);

			mstate->gpr[rt(instr)] = y;
			return nothing_special;
    		}
		case LBU:
    		{
			// Load Byte Unsigned
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate, va, data_load); //Shi yang 2006-08-10
			UInt32 y = 0;
			UInt32 x;
			load(mstate, va, pa, &y, 1);
			x = y & 0xffL; //Shi yang 2006-08-25
			mstate->gpr[rt(instr)] = x;

			return nothing_special;
    		}
		case LHU:
    		{
			// Load Halfword Unsigned
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bit(va, 0)) //Check alignment
		    		process_address_error(mstate,data_load, va);
			PA pa = translate_vaddr(mstate, va, data_load); //Shi yang 2006-08-10
			UInt16 x;
			UInt32 y = 0;
			load(mstate, va, pa, &y, 2);
			x = y & 0xffffL; //Shi yang 2006-08-25

			mstate->gpr[rt(instr)] = x;
			return nothing_special;
    		}
		case LWR:
    		{
			// Load Word Right
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate,va, data_load); //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);

			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			reg = copy_bits(reg, bits(mem, 31, syscmd * 8), 31 - syscmd * 8, 0);
			mstate->gpr[rt(instr)] = reg;
			return nothing_special;
    		}
		case LWU:
		{
			// Load Word Unsigned
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SB:
    		{
			// Store Byte
			if (mstate->sync_bit)
	    			sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate,va, data_store); //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 1); // Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
	    	case SH:
    		{
			// Store Halfword
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bit(va, 0)) //Check alignment
			    	process_address_error(mstate,data_store, va);
			PA pa = translate_vaddr(mstate, va, data_store); //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 2); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
		case SWL:
    		{
			// Store Word Left
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate, va, data_store); //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);
	
			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (!big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			mem = copy_bits(mem, bits(reg, 31, syscmd * 8), 31 - syscmd * 8, 0);
			store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case SW:
    		{
			// Store Word
			if (mstate->sync_bit)
		    		sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bits(va, 1, 0)) //Check alignment
			    	process_address_error(mstate,data_store, va);
			PA pa = translate_vaddr(mstate,va, data_store); //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case SDL:
    		{
			// Store Doubleword Left
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SDR:
    		{
			// Store Doubleword Right
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SWR:
    		{
			// Store Word Right
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa = translate_vaddr(mstate, va, data_store); //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate,round_down(va, 4), round_down(pa, 4),&y,4);
			mem = y & (0xffffffff);
	
			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			mem = copy_bits(mem, reg, 31, syscmd * 8);
			store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case CACHE: //Nedved's cache instruction. Shi yang 2006-08-24
    		{
			// Cache
			return nothing_special;
    		}
		case LL:
    		{
			// Load Linked
			int va = mstate->gpr[base(instr)] + offset(instr);
			PA pa = translate_vaddr(mstate, va, data_load);
			int data;
			mips_mem_read(pa, &data, 4);	
			mstate->gpr[rt(instr)] = data;
			//process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case LWC1:
    		{
			// Load Word to Coprocessor 1
			return nothing_special; //Shi yang 2006-08-31
    		}
	    	case LWC2:
    		{
			// Load Word to Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case LLD:
    		{
			// Load Linked Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDC1:
    		{
			// Load Doubleword To Coprocessor 1
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case LDC2:
    		{
			// Load Doubleword To Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LD:
    		{
			// Load Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SC:
    		{
			// Store Conditional
                        int va = mstate->gpr[base(instr)] + offset(instr);
                        PA pa = translate_vaddr(mstate, va, data_load);
                        int data;
			data = mstate->gpr[rt(instr)];
                        mips_mem_write(pa, &data, 4);
                        mstate->gpr[rt(instr)] = 1;

			//process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SWC1:
    		{
			// Store Word From Coprocessor 1
			return nothing_special; //Shi yang 2006-08-31
    		}
		case SWC2:
    		{
			// Store Word From Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SCD:
    		{
			// Store Conditional
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SDC1:
    		{
			// Store Doubleword From Coprocessor 1
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case SDC2:
    		{
			// Store Doubleword From Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SD:
    		{
			// Store Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		default:
			// Reserved instruction.
			process_reserved_instruction(mstate);
			return nothing_special;
    	}
}