hublb.h

ARM S3C2410 linux2.4 内核源码

 *  These registers are scratch registers that are not reset. At a      *
 * register's normal address, it is a simple storage location. At a     *
 * register's Write-If-Zero address, it accepts a new value from a      *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg1_wz_u {
	bdrkreg_t	lb_scratch_reg1_wz_regval;
	struct  {
		bdrkreg_t	srw_scratch_bits          :	64;
	} lb_scratch_reg1_wz_fld_s;
} lb_scratch_reg1_wz_u_t;




/************************************************************************
 *                                                                      *
 *  These registers are scratch registers that are not reset. At a      *
 * register's normal address, it is a simple storage location. At a     *
 * register's Write-If-Zero address, it accepts a new value from a      *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg2_wz_u {
	bdrkreg_t	lb_scratch_reg2_wz_regval;
	struct  {
		bdrkreg_t	srw_scratch_bits          :	64;
	} lb_scratch_reg2_wz_fld_s;
} lb_scratch_reg2_wz_u_t;




/************************************************************************
 *                                                                      *
 *  These one-bit registers are scratch registers. At a register's      *
 * normal address, it is a simple storage location. At a register's     *
 * Read-Set-If-Zero address, it returns the original contents and       *
 * sets the bit if the original value is zero.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_scratch_reg3_rz_u {
	bdrkreg_t	lb_scratch_reg3_rz_regval;
	struct  {
		bdrkreg_t	srr_scratch_bit           :	 1;
		bdrkreg_t       srr_reserved              :     63;
	} lb_scratch_reg3_rz_fld_s;
} lb_scratch_reg3_rz_u_t;

#else

typedef union lb_scratch_reg3_rz_u {
	bdrkreg_t	lb_scratch_reg3_rz_regval;
	struct	{
		bdrkreg_t	srr_reserved		  :	63;
		bdrkreg_t	srr_scratch_bit		  :	 1;
	} lb_scratch_reg3_rz_fld_s;
} lb_scratch_reg3_rz_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  These one-bit registers are scratch registers. At a register's      *
 * normal address, it is a simple storage location. At a register's     *
 * Read-Set-If-Zero address, it returns the original contents and       *
 * sets the bit if the original value is zero.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_scratch_reg4_rz_u {
	bdrkreg_t	lb_scratch_reg4_rz_regval;
	struct  {
		bdrkreg_t	srr_scratch_bit           :	 1;
		bdrkreg_t       srr_reserved              :     63;
	} lb_scratch_reg4_rz_fld_s;
} lb_scratch_reg4_rz_u_t;

#else

typedef union lb_scratch_reg4_rz_u {
	bdrkreg_t	lb_scratch_reg4_rz_regval;
	struct	{
		bdrkreg_t	srr_reserved		  :	63;
		bdrkreg_t	srr_scratch_bit		  :	 1;
	} lb_scratch_reg4_rz_fld_s;
} lb_scratch_reg4_rz_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register contains vector PIO parameters. A        *
 * write to this register triggers the LB to send out a vector PIO      *
 * request packet. Immediately after servicing a write request to the   *
 * LB_VECTOR_PARMS register, the LB sends back a reply (i.e., the LB    *
 * doesn't wait for the vector PIO operation to finish first). Three    *
 * LB registers provide the contents for an outgoing vector PIO         *
 * request packet. Software should wait until the BUSY bit in           *
 * LB_VECTOR_PARMS is clear and then initialize all three of these      *
 * registers before initiating a vector PIO operation. The three        *
 * vector PIO registers are:                                            *
 * LB_VECTOR_ROUTE                                                      *
 * LB_VECTOR_DATA                                                       *
 * LB_VECTOR_PARMS (should be written last)                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_vector_parms_u {
	bdrkreg_t	lb_vector_parms_regval;
	struct  {
		bdrkreg_t	vp_type                   :	 1;
		bdrkreg_t       vp_reserved_2             :      2;
		bdrkreg_t       vp_address                :     21;
		bdrkreg_t       vp_reserved_1             :      8;
		bdrkreg_t       vp_write_id               :      8;
		bdrkreg_t       vp_pio_id                 :     11;
		bdrkreg_t       vp_reserved               :     12;
		bdrkreg_t       vp_busy                   :      1;
	} lb_vector_parms_fld_s;
} lb_vector_parms_u_t;

#else

typedef union lb_vector_parms_u {
	bdrkreg_t	lb_vector_parms_regval;
	struct	{
		bdrkreg_t	vp_busy			  :	 1;
		bdrkreg_t	vp_reserved		  :	12;
		bdrkreg_t	vp_pio_id		  :	11;
		bdrkreg_t	vp_write_id		  :	 8;
		bdrkreg_t	vp_reserved_1		  :	 8;
		bdrkreg_t	vp_address		  :	21;
		bdrkreg_t	vp_reserved_2		  :	 2;
		bdrkreg_t	vp_type			  :	 1;
	} lb_vector_parms_fld_s;
} lb_vector_parms_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register contains the vector PIO route. This is one of the 3   *
 * vector PIO control registers.                                        *
 *                                                                      *
 ************************************************************************/




typedef union lb_vector_route_u {
	bdrkreg_t	lb_vector_route_regval;
	struct  {
		bdrkreg_t	vr_vector                 :	64;
	} lb_vector_route_fld_s;
} lb_vector_route_u_t;




/************************************************************************
 *                                                                      *
 *  This register contains the vector PIO write data. This is one of    *
 * the 3 vector PIO control registers. The contents of this register    *
 * also provide the data value to be sent in outgoing vector PIO read   *
 * requests and vector PIO write replies.                               *
 *                                                                      *
 ************************************************************************/




typedef union lb_vector_data_u {
	bdrkreg_t	lb_vector_data_regval;
	struct  {
		bdrkreg_t	vd_write_data             :	64;
	} lb_vector_data_fld_s;
} lb_vector_data_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This register contains the vector PIO return status.   *
 * Software should clear this register before launching a vector PIO    *
 * request from the LB. The LB will not modify this register's value    *
 * if an incoming reply packet encounters any kind of error. If an      *
 * incoming reply packet does not encounter an error but the            *
 * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
 * and leaves the other fields unchanged. The LB updates the values     *
 * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
 * an incoming vector PIO reply packet does not encounter an error      *
 * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
 * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
 * LB_VECTOR_READ_DATA registers.                                       *
 *                                                                      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_vector_status_u {
	bdrkreg_t	lb_vector_status_regval;
	struct  {
		bdrkreg_t	vs_type                   :	 3;
		bdrkreg_t       vs_address                :     21;
		bdrkreg_t       vs_reserved               :      8;
		bdrkreg_t       vs_write_id               :      8;
		bdrkreg_t       vs_pio_id                 :     11;
		bdrkreg_t       vs_source                 :     11;
		bdrkreg_t       vs_overrun                :      1;
		bdrkreg_t       vs_status_valid           :      1;
	} lb_vector_status_fld_s;
} lb_vector_status_u_t;

#else

typedef union lb_vector_status_u {
	bdrkreg_t	lb_vector_status_regval;
	struct	{
		bdrkreg_t	vs_status_valid		  :	 1;
		bdrkreg_t	vs_overrun		  :	 1;
		bdrkreg_t	vs_source		  :	11;
		bdrkreg_t	vs_pio_id		  :	11;
		bdrkreg_t	vs_write_id		  :	 8;
		bdrkreg_t	vs_reserved		  :	 8;
		bdrkreg_t	vs_address		  :	21;
		bdrkreg_t	vs_type			  :	 3;
	} lb_vector_status_fld_s;
} lb_vector_status_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register contains the return vector PIO route. The LB will     *
 * not modify this register's value if an incoming reply packet         *
 * encounters any kind of error. The LB also will not modify this       *
 * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
 * register is set when it receives an incoming vector PIO reply. The   *
 * LB stores an incoming vector PIO reply packet's vector route flit    *
 * in this register only if the packet does not encounter an error      *
 * and the STATUS_VALID bit is clear.                                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_vector_return_u {
	bdrkreg_t	lb_vector_return_regval;
	struct  {
		bdrkreg_t	vr_return_vector          :	64;
	} lb_vector_return_fld_s;
} lb_vector_return_u_t;




/************************************************************************
 *                                                                      *
 *  This register contains the vector PIO read data, if any. The LB     *
 * will not modify this register's value if an incoming reply packet    *
 * encounters any kind of error. The LB also will not modify this       *
 * register's value if the STATUS_VALID bit in the LB_VECTOR_STATUS     *
 * register is set when it receives an incoming vector PIO reply. The   *
 * LB stores an incoming vector PIO reply packet's data flit in this    *
 * register only if the packet does not encounter an error and the      *
 * STATUS_VALID bit is clear.                                           *
 *                                                                      *
 ************************************************************************/




typedef union lb_vector_read_data_u {
	bdrkreg_t	lb_vector_read_data_regval;
	struct  {
		bdrkreg_t	vrd_read_data             :	64;
	} lb_vector_read_data_fld_s;
} lb_vector_read_data_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This register contains the vector PIO return status.   *
 * Software should clear this register before launching a vector PIO    *
 * request from the LB. The LB will not modify this register's value    *
 * if an incoming reply packet encounters any kind of error. If an      *
 * incoming reply packet does not encounter an error but the            *
 * STATUS_VALID bit is already set, then the LB sets the OVERRUN bit    *
 * and leaves the other fields unchanged. The LB updates the values     *
 * of the SOURCE, PIO_ID, WRITE_ID, ADDRESS and TYPE fields only if     *
 * an incoming vector PIO reply packet does not encounter an error      *
 * and the STATUS_VALID bit is clear; at the same time, the LB sets     *
 * the STATUS_VALID bit and will also update the LB_VECTOR_RETURN and   *
 * LB_VECTOR_READ_DATA registers.                                       *
 *                                                                      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_vector_status_clear_u {
	bdrkreg_t	lb_vector_status_clear_regval;
	struct  {
		bdrkreg_t	vsc_type                  :	 3;
		bdrkreg_t       vsc_address               :     21;
		bdrkreg_t       vsc_reserved              :      8;
		bdrkreg_t       vsc_write_id              :      8;
		bdrkreg_t       vsc_pio_id                :     11;
		bdrkreg_t       vsc_source                :     11;
		bdrkreg_t       vsc_overrun               :      1;
		bdrkreg_t       vsc_status_valid          :      1;
	} lb_vector_status_clear_fld_s;
} lb_vector_status_clear_u_t;

#else

typedef union lb_vector_status_clear_u {
	bdrkreg_t	lb_vector_status_clear_regval;
	struct	{
		bdrkreg_t	vsc_status_valid	  :	 1;
		bdrkreg_t	vsc_overrun		  :	 1;
		bdrkreg_t	vsc_source		  :	11;
		bdrkreg_t	vsc_pio_id		  :	11;
		bdrkreg_t	vsc_write_id		  :	 8;
		bdrkreg_t	vsc_reserved		  :	 8;
		bdrkreg_t	vsc_address		  :	21;
		bdrkreg_t	vsc_type		  :	 3;
	} lb_vector_status_clear_fld_s;
} lb_vector_status_clear_u_t;

#endif






#endif /* _LANGUAGE_C */

/************************************************************************
 *                                                                      *
 *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
 *                                                                      *
 ************************************************************************/





#endif /* _ASM_SN_SN1_HUBLB_H */