vspi.map.rpt

FPGA/CPLD VHDL语言实现SPI

;     -- Total 2-input functions    ; 16      ;
;     -- Total 1-input functions    ; 6       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 45      ;
; Total logic cells in carry chains ; 5       ;
; I/O pins                          ; 39      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 45      ;
; Total fan-out                     ; 464     ;
; Average fan-out                   ; 2.96    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                      ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                          ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+
; |vspi                              ; 118 (114)   ; 45           ; 0           ; 39   ; 73 (69)      ; 5 (5)             ; 40 (40)          ; 5 (1)           ; 0 (0)      ; |vspi                                                        ;
;    |lpm_add_sub:Add1|              ; 4 (0)       ; 0            ; 0           ; 0    ; 4 (0)        ; 0 (0)             ; 0 (0)            ; 4 (0)           ; 0 (0)      ; |vspi|lpm_add_sub:Add1                                       ;
;       |addcore:adder|              ; 4 (1)       ; 0            ; 0           ; 0    ; 4 (1)        ; 0 (0)             ; 0 (0)            ; 4 (1)           ; 0 (0)      ; |vspi|lpm_add_sub:Add1|addcore:adder                         ;
;          |a_csnbuffer:result_node| ; 3 (3)       ; 0            ; 0           ; 0    ; 3 (3)        ; 0 (0)             ; 0 (0)            ; 3 (3)           ; 0 (0)      ; |vspi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 45    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add1 ;
+------------------------+-------------+----------------------------+
; Parameter Name         ; Value       ; Type                       ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH              ; 5           ; Untyped                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                    ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                    ;
; LPM_PIPELINE           ; 0           ; Untyped                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH         ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                    ;
; USE_WYS                ; OFF         ; Untyped                    ;
; STYLE                  ; FAST        ; Untyped                    ;
; CBXI_PARAMETER         ; add_sub_rah ; Untyped                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE             ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Dec 07 17:29:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vspi -c vspi
Info: Found 3 design units, including 1 entities, in source file vspi.vhd
    Info: Found design unit 1: vspi-empty
    Info: Found design unit 2: vspi-rtl
    Info: Found entity 1: vspi
Info: Elaborating entity "vspi" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add1|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add1"
Info: Instantiated megafunction "lpm_add_sub:Add1" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Implemented 157 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 21 output pins
    Info: Implemented 118 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Dec 07 17:29:37 2007
    Info: Elapsed time: 00:00:10