vspi.tan.qmsg

FPGA/CPLD VHDL语言实现SPI

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 235 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dvd_ctr\[2\] register shift_reg\[0\] 53.48 MHz 18.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 53.48 MHz between source register \"dvd_ctr\[2\]\" and destination register \"shift_reg\[0\]\" (period= 18.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.900 ns + Longest register register " "Info: + Longest register to register delay is 16.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dvd_ctr\[2\] 1 REG LC1_F38 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F38; Fanout = 3; REG Node = 'dvd_ctr\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dvd_ctr[2] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 536 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 2.800 ns Equal5~43 2 COMB LC3_F40 1 " "Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC3_F40; Fanout = 1; COMB Node = 'Equal5~43'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { dvd_ctr[2] Equal5~43 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.700 ns Equal5~44 3 COMB LC1_F40 5 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.700 ns; Loc. = LC1_F40; Fanout = 5; COMB Node = 'Equal5~44'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Equal5~43 Equal5~44 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 7.500 ns shift_clk_negedge~34 4 COMB LC6_F41 2 " "Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 7.500 ns; Loc. = LC6_F41; Fanout = 2; COMB Node = 'shift_clk_negedge~34'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { Equal5~44 shift_clk_negedge~34 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 308 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 9.600 ns shift_clk~51 5 COMB LC1_F41 7 " "Info: 5: + IC(0.200 ns) + CELL(1.900 ns) = 9.600 ns; Loc. = LC1_F41; Fanout = 7; COMB Node = 'shift_clk~51'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { shift_clk_negedge~34 shift_clk~51 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 11.500 ns shift_reg~858 6 COMB LC2_F41 8 " "Info: 6: + IC(0.200 ns) + CELL(1.700 ns) = 11.500 ns; Loc. = LC2_F41; Fanout = 8; COMB Node = 'shift_reg~858'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { shift_clk~51 shift_reg~858 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.200 ns) 13.800 ns shift_reg~899 7 COMB LC3_F42 1 " "Info: 7: + IC(1.100 ns) + CELL(1.200 ns) = 13.800 ns; Loc. = LC3_F42; Fanout = 1; COMB Node = 'shift_reg~899'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { shift_reg~858 shift_reg~899 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 15.700 ns shift_reg~878 8 COMB LC4_F42 1 " "Info: 8: + IC(0.000 ns) + CELL(1.900 ns) = 15.700 ns; Loc. = LC4_F42; Fanout = 1; COMB Node = 'shift_reg~878'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { shift_reg~899 shift_reg~878 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 16.900 ns shift_reg\[0\] 9 REG LC6_F42 3 " "Info: 9: + IC(0.200 ns) + CELL(1.000 ns) = 16.900 ns; Loc. = LC6_F42; Fanout = 3; REG Node = 'shift_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.800 ns ( 75.74 % ) " "Info: Total cell delay = 12.800 ns ( 75.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns ( 24.26 % ) " "Info: Total interconnect delay = 4.100 ns ( 24.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.900 ns" { dvd_ctr[2] Equal5~43 Equal5~44 shift_clk_negedge~34 shift_clk~51 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.900 ns" { dvd_ctr[2] Equal5~43 Equal5~44 shift_clk_negedge~34 shift_clk~51 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.100ns 0.000ns 0.200ns } { 0.000ns 1.700ns 1.700ns 1.700ns 1.900ns 1.700ns 1.200ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns shift_reg\[0\] 2 REG LC6_F42 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_F42; Fanout = 3; REG Node = 'shift_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk shift_reg[0] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out shift_reg[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns dvd_ctr\[2\] 2 REG LC1_F38 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_F38; Fanout = 3; REG Node = 'dvd_ctr\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk dvd_ctr[2] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 536 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk dvd_ctr[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out dvd_ctr[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out shift_reg[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk dvd_ctr[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out dvd_ctr[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 536 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.900 ns" { dvd_ctr[2] Equal5~43 Equal5~44 shift_clk_negedge~34 shift_clk~51 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.900 ns" { dvd_ctr[2] Equal5~43 Equal5~44 shift_clk_negedge~34 shift_clk~51 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.100ns 0.000ns 0.200ns } { 0.000ns 1.700ns 1.700ns 1.700ns 1.900ns 1.700ns 1.200ns 1.900ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out shift_reg[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk dvd_ctr[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out dvd_ctr[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "shift_reg\[0\] write clk 20.100 ns register " "Info: tsu for register \"shift_reg\[0\]\" (data pin = \"write\", clock pin = \"clk\") is 20.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.300 ns + Longest pin register " "Info: + Longest pin to register delay is 21.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns write 1 PIN PIN_65 4 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_65; Fanout = 4; PIN Node = 'write'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { write } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 240 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.700 ns) 8.500 ns spi_go~17 2 COMB LC2_F31 4 " "Info: 2: + IC(3.700 ns) + CELL(1.700 ns) = 8.500 ns; Loc. = LC2_F31; Fanout = 4; COMB Node = 'spi_go~17'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { write spi_go~17 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 316 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.700 ns) 12.300 ns spi_go~18 3 COMB LC1_F51 9 " "Info: 3: + IC(2.100 ns) + CELL(1.700 ns) = 12.300 ns; Loc. = LC1_F51; Fanout = 9; COMB Node = 'spi_go~18'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { spi_go~17 spi_go~18 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 316 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.000 ns) 15.900 ns shift_reg~858 4 COMB LC2_F41 8 " "Info: 4: + IC(1.600 ns) + CELL(2.000 ns) = 15.900 ns; Loc. = LC2_F41; Fanout = 8; COMB Node = 'shift_reg~858'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { spi_go~18 shift_reg~858 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.200 ns) 18.200 ns shift_reg~899 5 COMB LC3_F42 1 " "Info: 5: + IC(1.100 ns) + CELL(1.200 ns) = 18.200 ns; Loc. = LC3_F42; Fanout = 1; COMB Node = 'shift_reg~899'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { shift_reg~858 shift_reg~899 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 20.100 ns shift_reg~878 6 COMB LC4_F42 1 " "Info: 6: + IC(0.000 ns) + CELL(1.900 ns) = 20.100 ns; Loc. = LC4_F42; Fanout = 1; COMB Node = 'shift_reg~878'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { shift_reg~899 shift_reg~878 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 305 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 21.300 ns shift_reg\[0\] 7 REG LC6_F42 3 " "Info: 7: + IC(0.200 ns) + CELL(1.000 ns) = 21.300 ns; Loc. = LC6_F42; Fanout = 3; REG Node = 'shift_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.600 ns ( 59.15 % ) " "Info: Total cell delay = 12.600 ns ( 59.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 40.85 % ) " "Info: Total interconnect delay = 8.700 ns ( 40.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.300 ns" { write spi_go~17 spi_go~18 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.300 ns" { write write~out spi_go~17 spi_go~18 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } { 0.000ns 0.000ns 3.700ns 2.100ns 1.600ns 1.100ns 0.000ns 0.200ns } { 0.000ns 3.100ns 1.700ns 1.700ns 2.000ns 1.200ns 1.900ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns shift_reg\[0\] 2 REG LC6_F42 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_F42; Fanout = 3; REG Node = 'shift_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk shift_reg[0] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out shift_reg[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.300 ns" { write spi_go~17 spi_go~18 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.300 ns" { write write~out spi_go~17 spi_go~18 shift_reg~858 shift_reg~899 shift_reg~878 shift_reg[0] } { 0.000ns 0.000ns 3.700ns 2.100ns 1.600ns 1.100ns 0.000ns 0.200ns } { 0.000ns 3.100ns 1.700ns 1.700ns 2.000ns 1.200ns 1.900ns 1.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk shift_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out shift_reg[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk mosio ctl_reg\[4\] 21.800 ns register " "Info: tco from clock \"clk\" to destination pin \"mosio\" through register \"ctl_reg\[4\]\" is 21.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 46 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 46; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns ctl_reg\[4\] 2 REG LC2_F37 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_F37; Fanout = 5; REG Node = 'ctl_reg\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk ctl_reg[4] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 434 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk ctl_reg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctl_reg[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 434 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.800 ns + Longest register pin " "Info: + Longest register to pin delay is 18.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctl_reg\[4\] 1 REG LC2_F37 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F37; Fanout = 5; REG Node = 'ctl_reg\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ctl_reg[4] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 434 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.000 ns) 3.200 ns shift_dataout~9 2 COMB LC2_F44 4 " "Info: 2: + IC(1.200 ns) + CELL(2.000 ns) = 3.200 ns; Loc. = LC2_F44; Fanout = 4; COMB Node = 'shift_dataout~9'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { ctl_reg[4] shift_dataout~9 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 312 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 6.900 ns mosio~25 3 COMB LC8_F39 1 " "Info: 3: + IC(1.800 ns) + CELL(1.900 ns) = 6.900 ns; Loc. = LC8_F39; Fanout = 1; COMB Node = 'mosio~25'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { shift_dataout~9 mosio~25 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 249 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(8.600 ns) 18.800 ns mosio 4 PIN PIN_142 0 " "Info: 4: + IC(3.300 ns) + CELL(8.600 ns) = 18.800 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'mosio'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.900 ns" { mosio~25 mosio } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 249 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns ( 66.49 % ) " "Info: Total cell delay = 12.500 ns ( 66.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 33.51 % ) " "Info: Total interconnect delay = 6.300 ns ( 33.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.800 ns" { ctl_reg[4] shift_dataout~9 mosio~25 mosio } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.800 ns" { ctl_reg[4] shift_dataout~9 mosio~25 mosio } { 0.000ns 1.200ns 1.800ns 3.300ns } { 0.000ns 2.000ns 1.900ns 8.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk ctl_reg[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out ctl_reg[4] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.800 ns" { ctl_reg[4] shift_dataout~9 mosio~25 mosio } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "18.800 ns" { ctl_reg[4] shift_dataout~9 mosio~25 mosio } { 0.000ns 1.200ns 1.800ns 3.300ns } { 0.000ns 2.000ns 1.900ns 8.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "addr\[0\] dataout\[7\] 19.400 ns Longest " "Info: Longest tpd from source pin \"addr\[0\]\" to destination pin \"dataout\[7\]\" is 19.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns addr\[0\] 1 PIN PIN_78 17 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 17; PIN Node = 'addr\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr[0] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 237 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 4.300 ns Mux0~2 2 COMB LC3_F44 1 " "Info: 2: + IC(1.800 ns) + CELL(2.000 ns) = 4.300 ns; Loc. = LC3_F44; Fanout = 1; COMB Node = 'Mux0~2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { addr[0] Mux0~2 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 575 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.000 ns) 8.100 ns Mux0~3 3 COMB LC7_F48 1 " "Info: 3: + IC(1.800 ns) + CELL(2.000 ns) = 8.100 ns; Loc. = LC7_F48; Fanout = 1; COMB Node = 'Mux0~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.800 ns" { Mux0~2 Mux0~3 } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 575 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(8.600 ns) 19.400 ns dataout\[7\] 4 PIN PIN_40 0 " "Info: 4: + IC(2.700 ns) + CELL(8.600 ns) = 19.400 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.300 ns" { Mux0~3 dataout[7] } "NODE_NAME" } } { "vspi.vhd" "" { Text "F:/QuartusII_work/vspi/vspi.vhd" 239 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.100 ns ( 67.53 % ) " "Info: Total cell delay = 13.100 ns ( 67.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 32.47 % ) " "Info: Total interconnect delay = 6.300 ns ( 32.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.400 ns" { addr[0] Mux0~2 Mux0~3 dataout[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "19.400 ns" { addr[0] addr[0]~out Mux0~2 Mux0~3 dataout[7] } { 0.000ns 0.000ns 1.800ns 1.800ns 2.700ns } { 0.000ns 0.500ns 2.000ns 2.000ns 8.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}