📄 vspi.sim.vwf

📁 FPGA/CPLD VHDL语言实现SPI
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 10000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("addr")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 2;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("addr[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "addr";
}

SIGNAL("addr[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "addr";
}

SIGNAL("datain")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("datain[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("datain[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "datain";
}

SIGNAL("dataout")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("dataout[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("dataout[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "dataout";
}

SIGNAL("write")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("chip_sel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("misoe")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("scko")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvsel")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("irq")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("mosii")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("rst")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("misoi")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("scki")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("tx_run")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("shift_reg")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("shift_reg[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("shift_reg[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "shift_reg";
}

SIGNAL("misoo")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("mosie")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("mosio")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("scke")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvsele")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvselo[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvselo[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvselo[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvselo[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("slvselo[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 1000;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("addr[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 9680.0;
	}
}

TRANSITION_LIST("addr[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 320.0;
		LEVEL 0 FOR 9680.0;
	}
}

TRANSITION_LIST("datain[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 960.0;
		LEVEL 0 FOR 8720.0;
	}
}

TRANSITION_LIST("datain[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 8720.0;
	}
}

TRANSITION_LIST("datain[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 8720.0;
	}
}

TRANSITION_LIST("datain[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 9200.0;
	}
}

TRANSITION_LIST("datain[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 9200.0;
	}
}

TRANSITION_LIST("datain[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 640.0;
		LEVEL 0 FOR 9040.0;
	}
}

TRANSITION_LIST("datain[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 160.0;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 800.0;
		LEVEL 0 FOR 8880.0;
	}
}

TRANSITION_LIST("datain[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 960.0;
		LEVEL 0 FOR 320.0;
		LEVEL 1 FOR 160.0;
		NODE
		{
			REPEAT = 26;
			LEVEL 0 FOR 160.0;
			LEVEL 1 FOR 160.0;
		}
		LEVEL 0 FOR 80.0;
	}
}

TRANSITION_LIST("dataout[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 335.3;
		LEVEL 1 FOR 3.8;
		LEVEL 0 FOR 16.4;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 9634.5;
	}
}

TRANSITION_LIST("dataout[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 334.0;
		LEVEL 1 FOR 2.0;
		LEVEL 0 FOR 18.3;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 9635.7;
	}
}

TRANSITION_LIST("dataout[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 23.5;
		LEVEL 1 FOR 151.6;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 2.3;
		LEVEL 0 FOR 17.3;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 9635.3;
	}
}

TRANSITION_LIST("dataout[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 355.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 9635.0;
	}
}

TRANSITION_LIST("dataout[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 355.2;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 970.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 3180.0;
		LEVEL 1 FOR 240.0;
		LEVEL 0 FOR 4890.0;
		LEVEL 1 FOR 114.8;
	}
}

TRANSITION_LIST("dataout[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 353.7;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 730.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 2940.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 4650.0;
		LEVEL 1 FOR 356.3;
	}
}

TRANSITION_LIST("dataout[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 23.0;
		LEVEL 1 FOR 155.3;
		LEVEL 0 FOR 157.7;
		LEVEL 1 FOR 2.0;
		LEVEL 0 FOR 17.2;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 250.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 2940.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 4650.0;
		LEVEL 1 FOR 480.0;
		LEVEL 0 FOR 354.8;
	}
}

TRANSITION_LIST("dataout[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 192.7;
		LEVEL 1 FOR 145.5;
		LEVEL 0 FOR 17.4;
		LEVEL 1 FOR 500.0;
		LEVEL 0 FOR 2930.0;
		LEVEL 1 FOR 490.0;
		LEVEL 0 FOR 4640.0;
		LEVEL 1 FOR 490.0;
		LEVEL 0 FOR 594.4;
	}
}

TRANSITION_LIST("write")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10000.0;
	}
}

TRANSITION_LIST("chip_sel")
{
	NODE
	{
		REPEAT = 1;
12 下一页
💿 文件大小 244 K
👤 上传用户 dongjunxi126
📂 所属分类嵌入式/单片机编程
🏷️ 相关标签

#FPGA #CPLD #VHDL #SPI
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