vspi.fit.summary

FPGA/CPLD VHDL语言实现SPI

Fitter Status : Successful - Fri Dec 07 17:30:04 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : vspi
Top-level Entity Name : vspi
Family : ACEX1K
Device : EP1K100QC208-3
Timing Models : Final
Total logic elements : 119 / 4,992 ( 2 % )
Total pins : 39 / 147 ( 27 % )
Total memory bits : 0 / 49,152 ( 0 % )
Total PLLs : 0