vspi.map.summary

FPGA/CPLD VHDL语言实现SPI

Analysis & Synthesis Status : Successful - Fri Dec 07 17:29:37 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : vspi
Top-level Entity Name : vspi
Family : ACEX1K
Total logic elements : 118
Total pins : 39
Total memory bits : 0
Total PLLs : 0