vspi.tan.rpt

FPGA/CPLD VHDL语言实现SPI

Timing Analyzer report for vspi
Fri Dec 07 17:30:14 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. tpd
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                    ;
+------------------------------+-------+---------------+----------------------------------+------------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From       ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 20.100 ns                        ; write      ; shift_reg[0] ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 21.800 ns                        ; ctl_reg[4] ; mosio        ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 19.400 ns                        ; addr[0]    ; dataout[7]   ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.400 ns                        ; rst        ; ssel[6]      ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 53.48 MHz ( period = 18.700 ns ) ; dvd_ctr[2] ; shift_reg[6] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;            ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------+--------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K100QC208-3     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;