ms2_serial.cpp

PXA270平台下WINCE6.0的串口控制驱动

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

ms2_serial.cpp

Abstract:  
        MainstoneII BSP Serial Driver.

Notes: 


--*/
#include <windows.h>
#include <types.h>
#include <ceddk.h>

#include <ddkreg.h>
#include <serhw.h>
#include <hw16550.h>
#include <Serdbg.h>

#include <bulverde.h>
#include <xllp_gpio.h>
#include <BUL16550.h>

#include <mainstoneii.h>
#include <xllp_bcr.h>

#include <notify.h>
#include <bsp.h>

BOOL IsDebugSerialPort(UINT32 port_PA)
{
    static BSP_ARGS *pArgs = NULL;

    if (pArgs == NULL)
    {
        PHYSICAL_ADDRESS ioPhysBase = {IMAGE_SHARE_ARGS_PA_START, 0};
        pArgs = (BSP_ARGS*) MmMapIoSpace(ioPhysBase, sizeof(*pArgs), FALSE);
        if( pArgs == NULL )
        {
            NKDbgPrintfW(TEXT("MS2_Serial: IsDebugSerialPort: Failed to map BSP ARGS!\r\n"));
            return TRUE;
        }
    }
    return ( port_PA == pArgs->dbgSerPhysAddr );    
}

//---------------------------------Individual UART PORT -----------------------------------
//---------------------------------FUART PORT -----------------------------------
class CBulPdd16550FUART : public CBulPdd16550 {
public:
    CBulPdd16550FUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj) {  };
    virtual BOOL Init() {
        if (IsDebugSerialPort(BULVERDE_BASE_REG_PA_FFUART) ) {
            NKDbgPrintfW(TEXT("MS2_Serial: Init: FAIL: FFUART is already in use for serial debug logging. Disabling Driver!\r\n"));
            return FALSE;
        }
        if (CBulPdd16550::Init() ) {
            ConfigurePinout();
            //Enable FFUART clock
            m_pDCCLKReg->cken |= XLLP_CLKEN_FFUART ;
            return TRUE;
        }
        else
            return FALSE;
    }

    virtual void CBulPdd16550FUART::PostInit()
    {
        CBulPdd16550::PostInit();

        //Clear/Enable interrupts and UART to take care of rx data without COM_Open()
        //so that event "NOTIFICATION_EVENT_RS232_DETECTED" get chance to be notified

        //RETAILMSG(TRUE, (TEXT("Enable interrupts and UART to take care of rx data without COM_Open().\r\n")));
        m_HardwareLock.Lock();   
        BYTE bIER = GetRegister()->Read_IER();
        GetRegister()->Write_IER(bIER | BUL_SERIAL_IER_UUE);

#if AUTODETECT_USING_DSR
        BYTE bMSR = GetRegister()->Read_MSR(); // Clears MSR
        if (bMSR & (SERIAL_MSR_DDSR | SERIAL_MSR_DCTS | SERIAL_MSR_TERI | SERIAL_MSR_DDCD) ) {
            RETAILMSG(TRUE, (TEXT("MS2_Serial: PostInit: Ignoring previous serial pin states to prevent accidental auto-launch of applications. Re-plug serial cable for hot-plug functionality\r\n")));
        }
#endif // end #if AUTODETECT_USING_DSR

        m_HardwareLock.Unlock();

    }

    virtual ULONG   CBulPdd16550FUART::GetModemStatus()
    {
        m_HardwareLock.Lock();    
        ULONG ulReturn =0 ;
        ULONG Events = 0;
        UINT8 ubModemStatus = GetRegister()->Read_MSR();
        m_HardwareLock.Unlock();

        // Event Notification.
        if (ubModemStatus & SERIAL_MSR_DCTS)
            Events |= EV_CTS;
        if ( ubModemStatus  & SERIAL_MSR_DDSR )
            Events |= EV_DSR;
        if ( ubModemStatus  & SERIAL_MSR_TERI )
            Events |= EV_RING;
        if ( ubModemStatus  & SERIAL_MSR_DDCD )
            Events |= EV_RLSD;

        // Report Modem Status;
        if ( ubModemStatus & SERIAL_MSR_CTS )
            ulReturn |= MS_CTS_ON;
        if ( ubModemStatus & SERIAL_MSR_DSR )
            ulReturn |= MS_DSR_ON;
        if ( ubModemStatus & SERIAL_MSR_RI )
            ulReturn |= MS_RING_ON;
        if ( ubModemStatus & SERIAL_MSR_DCD )
            ulReturn |= MS_RLSD_ON;

        if (Events!=0)
            EventCallback(Events,ulReturn);
        
#if AUTODETECT_USING_DSR
        // DCD signal is incorrect on some boards: is always LOW and never changes
        // This works around is to detect DSR signal instead
        // as DSR & CD are jumpered for serial null-modem cable (DB9-DB9).
        if (!IsOpen() && ((Events & EV_DSR)!=0 && (ulReturn & MS_DSR_ON)!=0))
        {
            CeEventHasOccurred (NOTIFICATION_EVENT_RS232_DETECTED, NULL);
        }
#endif // end #if AUTODETECT_USING_DSR

        return ulReturn;
    }

    virtual BOOL  CBulPdd16550FUART::Close()
    {
        BOOL bReturn =  CBulPdd16550::Close();
        if (bReturn) { 

            //Enable interrupts and UART to take care of rx data without COM_Open()
            //so that event "NOTIFICATION_EVENT_RS232_DETECTED" get chance to be notified
            m_HardwareLock.Lock();   
            GetRegister()->Write_IER(GetRegister()->Read_IER() |  BUL_SERIAL_IER_UUE);
            m_HardwareLock.Unlock();
        }
        return bReturn;
    }

    virtual void    SerialRegisterRestore() {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
    }

private:
    BOOL ConfigurePinout(){
        //Initialize GPIO pins 
        //Write 0 on GPIO pins 39, 40 and 41 before configuring them as outputs.
        m_pGPIOReg->GPCR1 = ( XLLP_GPIO_BIT_FFDTR | XLLP_GPIO_BIT_FFTXD | XLLP_GPIO_BIT_FFRTS );
        
        //Configure direction of GPIO pins 34, 35, 36, 37 and 38 as input 
        //and GPIO pins 39, 40 and 41 as output
        m_pGPIOReg->GPDR1 &= ~( XLLP_GPIO_BIT_FFRXD | XLLP_GPIO_BIT_FFCTS | 
                                XLLP_GPIO_BIT_FFDCD | XLLP_GPIO_BIT_FFDSR | 
                                XLLP_GPIO_BIT_FFRI );
        m_pGPIOReg->GPDR1 |= (  XLLP_GPIO_BIT_FFTXD |  XLLP_GPIO_BIT_FFDTR |  XLLP_GPIO_BIT_FFRTS );
        
        //Configure GPIO pins 34, 35, 36, 37 and 38 for Alt_fn1. And pins 39, 40 and 41 for Alt_fn2.
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_FFRXD | XLLP_GPIO_AF_BIT_FFCTS | 
                                XLLP_GPIO_AF_BIT_FFDCD | XLLP_GPIO_AF_BIT_FFDSR | 
                                XLLP_GPIO_AF_BIT_FFRI  | XLLP_GPIO_AF_BIT_FFTXD | 
                                XLLP_GPIO_AF_BIT_FFDTR | XLLP_GPIO_AF_BIT_FFRTS );

#if CLEAR_GPIO33_AF

        if ( ((m_pGPIOReg->GAFR1_L & XLLP_GPIO_AF_BIT_nCS5_MASK) == XLLP_GPIO_AF_BIT_nCS5)
            && ((m_pGPIOReg->GPDR1 & XLLP_GPIO_BIT_nCS5) == 0))
        {
            // Need to clear GPIO#33 Altternate Function to be zero,
            // because currently in StartUp() of OAL, default value will set GPIO#33 as Input AF 2 (FFDSR).
            // 2 FFDSR caused no FFDSR interrupt is generated.
            

            m_pGPIOReg->GAFR1_L &= ~(XLLP_GPIO_AF_BIT_nCS5_MASK);
        }

#endif // end #if CLEAR_GPIO33_AF

        return TRUE;
    }
};
//---------------------------------BUART PORT -----------------------------------
class CBulPdd16550BUART : public CBulPdd16550 {
public:
    CBulPdd16550BUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj) 
    { 
        m_pBCRReg = NULL;     
    };
    ~CBulPdd16550BUART() {
        if (m_pBCRReg)
            MmUnmapIoSpace(m_pBCRReg,0);
    }
    
    virtual BOOL Init() {
        if (IsDebugSerialPort(BULVERDE_BASE_REG_PA_BTUART) ) {
            NKDbgPrintfW(TEXT("MS2_Serial: Init: FAIL: BTUART is already in use for serial debug logging. Disabling Driver!\r\n"));
            return FALSE;
        }
        if (m_pBCRReg==NULL) {
            PHYSICAL_ADDRESS ioPhysicalBase = { MAINSTONEII_BASE_REG_PA_FPGA, 0 };
            m_pBCRReg =(PMAINSTONEII_BLR_REGS) MmMapIoSpace(ioPhysicalBase, sizeof(MAINSTONEII_BLR_REGS),FALSE) ;
        }
            
        if (m_pBCRReg!=NULL && CBulPdd16550::Init()) {
            ConfigurePinout();
            //Enable BTUART clock
            m_pDCCLKReg->cken |= XLLP_CLKEN_BTUART ;
            return TRUE;
        }
        else
            return FALSE;
    }
    virtual void    SerialRegisterRestore() {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
    }
    virtual void    SetDTR(BOOL bSet) {
        if (bSet)
            m_pBCRReg->misc_wr &= ~XLLP_BCR_MISCWR1_BTDTR; 
        else
            m_pBCRReg->misc_wr |= XLLP_BCR_MISCWR1_BTDTR; 
            
    }
private:
    BOOL ConfigurePinout() {
        //Configuring GPIO pins for BTUART
        //Initialize GPIO pins 
        //Write 0 on GPIO pins 43 and 45 before configuring them as outputs.
        m_pGPIOReg->GPCR1 = (XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);

        //Configure direction of GPIO pins 42 and 44 as input 
        //and GPIO pins 43 and 45 as output
        m_pGPIOReg->GPDR1 &= ~( XLLP_GPIO_BIT_BTRXD | XLLP_GPIO_BIT_BTCTS); 
        m_pGPIOReg->GPDR1 |=  ( XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);


        //Configure GPIO pins 42 and 44 for Alt_fn1. And pins 43 and 45 for Alt_fn2.
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_BTRXD | XLLP_GPIO_AF_BIT_BTCTS |
                                XLLP_GPIO_AF_BIT_BTTXD | XLLP_GPIO_AF_BIT_BTRTS );


        //Turn on the BTUART transceiver
        m_pBCRReg->misc_wr |= XLLP_BCR_MISCWR1_nBT_OFF; 

        return TRUE;
    }
    volatile PMAINSTONEII_BLR_REGS m_pBCRReg;
};
//---------------------------------FUART PORT -----------------------------------
class CBulPdd16550SUART : public CBulPdd16550 {
public:
    CBulPdd16550SUART (LPTSTR lpActivePath, PVOID pMdd, PHWOBJ pHwObj) 
        : CBulPdd16550 (lpActivePath,pMdd, pHwObj)
    { 
        m_pBCRReg = NULL;     
    };
    ~CBulPdd16550SUART()
    {
        if (m_pBCRReg)
            MmUnmapIoSpace(m_pBCRReg,0);
    }
    virtual BOOL Init() {
        if (IsDebugSerialPort(BULVERDE_BASE_REG_PA_STUART) ) {
            NKDbgPrintfW(TEXT("MS2_Serial: Init: FAIL: STUART is already in use for serial debug logging. Disabling Driver!\r\n"));
            return FALSE;
        }
        if (m_pBCRReg==NULL) {
            PHYSICAL_ADDRESS ioPhysicalBase = { MAINSTONEII_BASE_REG_PA_FPGA, 0 };
            m_pBCRReg =(PMAINSTONEII_BLR_REGS) MmMapIoSpace(ioPhysicalBase, sizeof(MAINSTONEII_BLR_REGS),FALSE);
        }
        if (m_pBCRReg!=NULL  && CBulPdd16550::Init()){
            ConfigurePinout();
            m_pDCCLKReg->cken |= XLLP_CLKEN_STUART ;
            return TRUE;
        }
        else
            return FALSE;
    }
    virtual void    SerialRegisterRestore() {
        ConfigurePinout();
        CBulPdd16550::SerialRegisterRestore();
        
    }

private:
    BOOL ConfigurePinout() {
        //Initialize GPIO pins 
        //Write 0 on GPIO pin 47 before configuring it as output.
        //Verify whether to write zero or not?
        //pHWHead->pGPIOReg->GPCR_y |=  (GPIO_47);
        m_pGPIOReg->GPSR1 =  (XLLP_GPIO_BIT_STD_TXD);

        //Configure direction of GPIO pin 46 as input and GPIO pin 47 as output
        m_pGPIOReg->GPDR1 &= (~XLLP_GPIO_BIT_STD_RXD);
        m_pGPIOReg->GPDR1 |= ( XLLP_GPIO_BIT_STD_TXD);

        //Configure GPIO pin 46 for Alt_fn2. And, GPIO pin 47 for Alt_fn1.
        m_pGPIOReg->GAFR1_L |= (XLLP_GPIO_AF_BIT_STD_RXD | XLLP_GPIO_AF_BIT_STD_TXD);

        //Configure IrDA transceiver for SIR mode and full distance power.  
        //pHWHead->pBCRReg->misc_wr &= ~(IRDA_MD_MASK | IRDA_FIR_MASK);
        m_pBCRReg->misc_wr &= (~XLLP_BCR_MISCWR1_IRDA_MD & ~XLLP_BCR_MISCWR1_IRDA_FIR);

        return TRUE;
    }

    volatile PMAINSTONEII_BLR_REGS m_pBCRReg;
};
CSerialPDD * CreateSerialObject(LPTSTR lpActivePath, PVOID pMdd,PHWOBJ pHwObj, DWORD DeviceArrayIndex)
{
    CSerialPDD * pSerialPDD = NULL;
    switch (DeviceArrayIndex ) {
        case 0:default:
            pSerialPDD = new CPdd16550(lpActivePath,pMdd, pHwObj);
            break;
        case 0x80:
            pSerialPDD = new CBulPdd16550FUART (lpActivePath,pMdd, pHwObj);
            break;
        case 0x81:
            pSerialPDD = new CBulPdd16550BUART(lpActivePath,pMdd, pHwObj);
            break;
        case 0x82:
            pSerialPDD = new CBulPdd16550SUART(lpActivePath,pMdd, pHwObj);
            break;
    }
    if (pSerialPDD && pSerialPDD->Init()!= TRUE) {
        delete pSerialPDD;
        pSerialPDD = NULL;
    }
    return pSerialPDD;
}
void DeleteSerialObject(CSerialPDD * pSerialPDD)
{
    if (pSerialPDD)
        delete pSerialPDD;
}