dacsine.asm

ADUC824单片机的片内DAC转换程序

;********************************************************************
;
; Author        : ADI - Apps            www.analog.com/MicroConverter
;
; Date          : 30 Sept 1999
;
; File          : DACsin824.asm
;
; Hardware      : ADuC824
;
; Description   : DAC outputs a sine wave 1.1kHz to pin 12.
;                 Rate calculations assume an 32.768kHz crystal
;		  producing a core frequency of 12.58MHz.
;
;********************************************************************

$MOD824                         ; Use 8052&ADuC824 predefined symbols

LED     EQU     P3.4            ; P3.4 drives red LED on eval board

;____________________________________________________________________
                                                  ; BEGINNING OF CODE
CSEG

ORG 0000h

	MOV	PLLCON, #00H   ; set core frequency to 12.58MHz

        MOV     DACCON,#03h    ; Configure DAC with
                               ; DAC on
                               ; 12bit
                               ; o/p @ pin 10
                               ; Range 0-> Vref (2.5V internal ref)
       
        MOV     DACH,#08h      ; DAC to mid-scale (1.25V) to start 
        MOV     DACL,#00h      ; transmissions from mid-scale 


        MOV     DPTR, #TABLE

STEP:   CLR     A              ;                                   1
        MOVC    A,@A+DPTR      ; get high data byte from table..   2
        MOV     DACH,A         ; ..and move it into DAC register   1
        INC     DPTR           ; move on to get low byte           2

        CLR     A              ;                                   1
        MOVC    A,@A+DPTR      ; get low data byte from table..    2
        MOV     DACL,A         ; ..and update DAC output           1
        INC     DPTR           ; move on for next data point       2
 
        MOV     A, DPL         ; Check if DPL=80h, if so then the  1
        CJNE    A,#80h,STEP    ; table has been outputted and we   2                              
        MOV     DPTR, #TABLE   ; should reset the DPTR to 1000h    
        CPL     LED            ; and start outputting data again   

        JMP     STEP           ;                                   

; Numbers at right in the above loop represent the number of machine
; cycles for each instruction.  The typical loop ends after the CJNE
; command thus requiring 15 machine cycles.
; With a  12.583MHz master clock, a machine cycle takes 0.953us to 
; execute, so the above loop takes 14.3us to update each data point.
; Since there are 64 data points in the below sine lookup table, 
; this results in a 915us period, i.e. a 1.1kHz frequency.

;____________________________________________________________________
                                                  ; SINE LOOKUP TABLE
ORG 01000h

TABLE:

DB  007h, 0FFh
DB  008h, 0C8h
DB  009h, 08Eh
DB  00Ah, 051h
DB  00Bh, 00Fh
DB  00Bh, 0C4h
DB  00Ch, 071h
DB  00Dh, 012h
DB  00Dh, 0A7h
DB  00Eh, 02Eh
DB  00Eh, 0A5h
DB  00Fh, 00Dh
DB  00Fh, 063h
DB  00Fh, 0A6h
DB  00Fh, 0D7h
DB  00Fh, 0F5h
DB  00Fh, 0FFh
DB  00Fh, 0F5h
DB  00Fh, 0D7h
DB  00Fh, 0A6h
DB  00Fh, 063h
DB  00Fh, 00Dh
DB  00Eh, 0A5h
DB  00Eh, 02Eh
DB  00Dh, 0A7h
DB  00Dh, 012h
DB  00Ch, 071h
DB  00Bh, 0C4h
DB  00Bh, 00Fh
DB  00Ah, 051h
DB  009h, 08Eh
DB  008h, 0C8h
DB  007h, 0FFh
DB  007h, 036h
DB  006h, 070h
DB  005h, 0ADh
DB  004h, 0EFh
DB  004h, 03Ah
DB  003h, 08Dh
DB  002h, 0ECh
DB  002h, 057h
DB  001h, 0D0h
DB  001h, 059h
DB  000h, 0F1h
DB  000h, 09Bh
DB  000h, 058h
DB  000h, 027h
DB  000h, 009h
DB  000h, 000h
DB  000h, 009h
DB  000h, 027h
DB  000h, 058h
DB  000h, 09Bh
DB  000h, 0F1h
DB  001h, 059h
DB  001h, 0D0h
DB  002h, 057h
DB  002h, 0ECh
DB  003h, 08Dh
DB  004h, 03Ah
DB  004h, 0EFh
DB  005h, 0ADh
DB  006h, 070h
DB  007h, 036h          ; end of table

;____________________________________________________________________

END