btvid2.c

developed under vxwork, support bt878 video card, use socket to stream video out.

}


int streamShutdown = 0;

void stream_client(void)
{
  mqd_t mymq;
  int prio;
  int nbytes;
  unsigned int frameNo = 0;

  init_frametx();

  /* note that VxWorks does not deal with permissions? */
  mymq = mq_open(SNDRCV_MQ, O_RDWR, 0, &mq_attr);

  if(mymq == (mqd_t)ERROR)
    perror("mq_open");


  taskPrioritySet(taskNameToId("tBtvid"), 0);
  taskPrioritySet(taskIdSelf(), 1);
  taskPrioritySet(taskNameToId("tNetTask"), 2);
  
  sysClkRateSet(60);

  start_frame_tx=1;
  enable_streaming=1;

  while(!streamShutdown)
  {

      /* semTake(streamRdy, WAIT_FOREVER); */

      /* read oldest, highest priority msg from the message queue */
      if((nbytes = mq_receive(mymq, (char *)frameNo, MAX_MSG_SIZE, &prio)) == ERROR)
      {
        perror("mq_receive");
      }
      else
      {
        frame_to_net(rgb_buffer);
      }
      
  }

}


void start_streaming(void)
{
    stream_tid = taskSpawn("tVidStream", 11, 0, (1024*8), (FUNCPTR) stream_client, 0,0,0,0,0,0,0,0,0,0);
}


int reset_status(void)
{
  unsigned int testval = 0;

  /* Clear the interrupt and status */
  PCI_READ(INT_STATUS_REG,0x0,&testval);

  PCI_WRITE(INT_STATUS_REG,0x0,0xFFFFFFFF);

  test_status();
}


int test_status(void)
{
  unsigned int testval = 0;

  PCI_READ(INT_STATUS_REG,0x0,&testval);
  logMsg("mmio INTSTATUS testval = 0x%x\n", testval,0,0,0,0,0);

  if(testval & 0x02000000)
    logMsg("I2C RACK\n",0,0,0,0,0,0);

  if(testval & 0x00000100)
    logMsg("I2C DONE\n",0,0,0,0,0,0);

  if(testval & 0x00000800)
    logMsg("RISC INT BIT SET\n",0,0,0,0,0,0);

  if(testval & (DMA_MC_WRITE<<12))
    logMsg("DMA_MC_WRITE\n",0,0,0,0,0,0);

  if(testval & (DMA_MC_SKIP<<12))
    logMsg("DMA_MC_SKIP\n",0,0,0,0,0,0);

  if(testval & (DMA_MC_JUMP<<12))
    logMsg("DMA_MC_JUMP\n",0,0,0,0,0,0);

  if(testval & (DMA_MC_SYNC<<12))
    logMsg("DMA_MC_SYNC\n",0,0,0,0,0,0);

  if(testval & 0x08000000)
    logMsg("DMA ENABLED\n",0,0,0,0,0,0);
  else
    logMsg("DMA DISABLED\n",0,0,0,0,0,0);

  if(testval & 0x01000000)
    logMsg("EVEN FIELD\n",0,0,0,0,0,0);
  else
    logMsg("ODD FIELD\n",0,0,0,0,0,0);

  if(testval & 0x00000020)
    logMsg("VIDEO PRESENT CHANGE DETECTED\n",0,0,0,0,0,0);

  if(testval & 0x00000010)
    logMsg("HLOCK CHANGE DETECTED\n",0,0,0,0,0,0);

  if(testval & 0x00000008)
    logMsg("LUMA/CHROMA OVERFLOW DETECTED\n",0,0,0,0,0,0);

  if(testval & 0x00000001)
    logMsg("PAL/NTSC FORMAT CHANGE DETECTED\n",0,0,0,0,0,0);

  if(testval & 0x00080000)
    logMsg("**** SYNC ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00040000)
    logMsg("**** DMA RISC ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00020000)
    logMsg("**** MASTER/TARGET ABORT ****\n",0,0,0,0,0,0);

  if(testval & 0x00010000)
    logMsg("**** DATA PARITY ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00008000)
    logMsg("**** PCI BUS PARITY ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00004000)
    logMsg("**** FIFO DATA RESYNC ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00002000)
    logMsg("**** FIFO OVERRUN ERROR ****\n",0,0,0,0,0,0);

  if(testval & 0x00001000)
    logMsg("**** BUS ACCESS LATENCY ERROR ****\n",0,0,0,0,0,0);

  PCI_READ(CAPTURE_CNT_REG,0x0,&testval);
  logMsg("mmio CAPTURE_CNT = 0x%x\n", testval,0,0,0,0,0,0);

  PCI_READ(DMA_RISC_PC_REG,0x0,&testval);
  logMsg("mmio DMA PC = 0x%x\n", testval,0,0,0,0,0,0);
}


int test_dmapc(void)
{
  unsigned int testval = 0;

  PCI_READ(DMA_RISC_PC_REG,0x0,&testval);
  printf("mmio DMA PC testval = 0x%x\n", testval);

}


void set_mux(int mux)
{
  unsigned int testval = 0x00000019; /* NTSC source */

  if(mux==0)
    testval |= 0x00000040;
  else if(mux==1)
    testval |= 0x00000060;
  else if(mux==2)
    testval |= 0x00000020;
  else if(mux==3)
    testval |= 0x00000000;
    
  /* Select NTSC source */
  PCI_WRITE(INPUT_REG,0x0,testval);

  printf("Setting INPUT_REG = 0x%x\n", testval);

}


int test_dstatus(void)
{
  unsigned int testval = 0;

  PCI_READ(BTVID_MMIO_ADDR,0x0,&testval);
  printf("mmio DSTATUS testval = 0x%x\n", testval);

  if(testval & 0x00000080)
    printf("**** VIDEO PRESENT\n");
  else
    printf("**** NO VIDEO\n");

  if(testval & 0x00000040)
    printf("**** HLOC ON\n");

  if(testval & 0x00000020)
    printf("**** DECODING EVEN FIELD\n");
  else
    printf("**** DECODING ODD FIELD\n");

  if(testval & 0x00000010)
    printf("**** 525 LINE NTSC FORMAT\n");

  if(testval & 0x00000004)
    printf("**** PLL OUT OF LOCK\n");

  if(testval & 0x00000002)
    printf("**** LUMA ADC OVERFLOW\n");

  if(testval & 0x00000001)
    printf("**** CHROMA ADC OVERFLOW\n");
}


int intel_pci_config(void)
{
	unsigned short int testval;
	unsigned int longword;
	unsigned char byte;

	int pciBusNo = PCI_DEV[NORTH_BRIDGE].busNo;
	int pciDevNo = PCI_DEV[NORTH_BRIDGE].deviceNo;
	int pciFuncNo = PCI_DEV[NORTH_BRIDGE].funcNo;
	int pciVenId = PCI_DEV[NORTH_BRIDGE].venId;
    	int pciDevId = PCI_DEV[NORTH_BRIDGE].devId;


	if(pciDevId == PCI_DEVICE_ID_INTEL_82441FX) {

		/* for 430 only
		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PCI_CTL, &byte);
		printf("Intel NB controller PCI concurrency enable = 0x%x\n", byte);

		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PCI_CTL, 0x00);
		printf("Modified Intel NB controller PCI concurrency enable = 0x%x\n", byte);
		*/

		/* Writting 0x00 to this register disables the check on how long the
		 * northbridge can stream data */
  
		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, &byte);
		printf("Intel NB controller PCI latency timer = 0x%x\n", byte);

		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, 0x00);
		printf("Modified Intel NB controller PCI latency timer = 0x%x\n", 0x00);

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, &byte);
		printf("Intel NB controller PCI latency timer = 0x%x\n\n", byte);

		/* Enable the North Bridge memory controller to allow memory access	
		   by another bus master.

		   MAE=1

		 */

		/* Not needed hardwired to 1 in the 82441FX 

		pciConfigInWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, &testval);
		printf("Intel NB controller PCI Cmd Reg = 0x%x\n", testval);

		pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0x0002);

		pciConfigInWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, &testval);
		printf("Modified Intel NB controller PCI Cmd Reg = 0x%x\n", testval);
		*/
  
		/* 430 only

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_ARB_CTL, &byte);
		printf("Intel NB controller PCI ARB CTL = 0x%x\n", byte);
		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_ARB_CTL, 0x80);
		printf("PCI 2.1 Compliant Intel NB controller PCI ARB CTL = 0x%x\n", byte);
		*/
	} else {

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PCI_CTL, &byte);
  		printf("Intel NB controller PCI concurrency enable = 0x%x\n", byte);

		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_PCI_CTL, 0x00);
		printf("Modified Intel NB controller PCI concurrency enable = 0x%x\n", byte);

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, &byte);
		printf("Intel NB controller PCI latency timer = 0x%x\n", byte);

		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, 0x00);
		printf("Modified Intel NB controller PCI latency timer = 0x%x\n", byte);

		/* Enable the North Bridge memory controller to allow memory access
		by another bus master.

		MAE=1

		*/

		pciConfigInWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, &testval);
		printf("Intel NB controller PCI Cmd Reg = 0x%x\n", testval);

		pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0x0002);

		pciConfigInWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, &testval);
		printf("Modified Intel NB controller PCI Cmd Reg = 0x%x\n", testval);

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_ARB_CTL, &byte);
		printf("Intel NB controller PCI ARB CTL = 0x%x\n", byte);
		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_ARB_CTL, 0x80);
		printf("PCI 2.1 Compliant Intel NB controller PCI ARB CTL = 0x%x\n", byte);		

	}


	pciBusNo = PCI_DEV[SOUTH_BRIDGE].busNo;
	pciDevNo = PCI_DEV[SOUTH_BRIDGE].deviceNo;
	pciFuncNo = PCI_DEV[SOUTH_BRIDGE].funcNo;
	pciVenId = PCI_DEV[SOUTH_BRIDGE].venId;
	pciDevId = PCI_DEV[SOUTH_BRIDGE].devId;

	if(pciDevId == PCI_DEVICE_ID_INTEL_82371SB_0) {	

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_CTL, &byte);
		printf("Intel SB controller latency control  = 0x%x\n", byte);
		byte |= 0x03;
		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_CTL, byte);
		printf("PCI 2.1 Compliant Intel SB controller latency control  = 0x%x\n", byte);
		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_CTL, &byte);
		printf("Intel SB controller latency control  = 0x%x\n\n", byte);



		/* IRQ Routing Setup */

		/*
		pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, &longword);
		printf("Intel SB controller IRQ Routing Reg = 0x%x\n", longword);

		longword = (((longword & 0x70FFFFFF) | ((BT878INT)<<24)) | 0x80000000);
		pciConfigOutLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, longword);
		pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, &longword);
		printf("Modified Intel SB controller IRQ Routing Reg = 0x%x\n", longword);
		*/

		/*  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_APIC_ADDR, &byte);
		printf("Intel SB controller APIC Addr Reg = 0x%x\n", byte);
		*/

	} else {

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_CTL, &byte);
		printf("Intel SB controller latency control  = 0x%x\n", byte);
		byte |= 0x03;
		pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_CTL, byte);
		printf("PCI 2.1 Compliant Intel SB controller latency control  = 0x%x\n", byte);

		pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, &longword);
		printf("Intel SB controller IRQ Routing Reg = 0x%x\n", longword);

		longword = (0x00808080 | ((BT878INT)<<24));

		pciConfigOutLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, longword);
  
		pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IRQ_ROUTING, &longword);
		printf("Modified Intel SB controller IRQ Routing Reg = 0x%x\n", longword);

		pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_APIC_ADDR, &byte);
		printf("Intel SB controller APIC Addr Reg = 0x%x\n", byte);	
	}

}


void intel_pci_clear_status(void)
{
  int pciBusNo = PCI_DEV[NORTH_BRIDGE].busNo;
  int pciDevNo = PCI_DEV[NORTH_BRIDGE].deviceNo;
  int pciFuncNo = PCI_DEV[NORTH_BRIDGE].funcNo;

  pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_STATUS, 0x3000);

}


void intel_pci_status(void)
{
  int pciBusNo = PCI_DEV[NORTH_BRIDGE].busNo;
  int pciDevNo = PCI_DEV[NORTH_BRIDGE].deviceNo;
  int pciFuncNo = PCI_DEV[NORTH_BRIDGE].funcNo;
  unsigned short int testval;

  pciConfigInWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_STATUS, &testval);
  printf("Intel NB controller PCI Status Reg = 0x%x\n", testval);
 
  if(testval & 0x1000)
    printf("**** INTEL NB TARGET ABORT ****\n");
 
  if(testval & 0x2000)
    printf("**** INTEL NB MASTER ABORT ****\n");

}



int btvid_controller_config(void)
{
  int pciBusNo = PCI_DEV[CAPTURE_VIDEO_CARD].busNo;
  int pciDevNo = PCI_DEV[CAPTURE_VIDEO_CARD].deviceNo;
  int pciFuncNo = PCI_DEV[CAPTURE_VIDEO_CARD].funcNo;

  int ix;
  unsigned int testval;
  unsigned short command = (BUS_MASTER_MMIO);
  unsigned char irq;
  unsigned char byte;

  /* Disable btvid */
  pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, 0);


  for (ix = PCI_CFG_BASE_ADDRESS_0; ix <= PCI_CFG_BASE_ADDRESS_5; ix+=4)
  {
      pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, ix, &testval);
      
      printf("BAR %d testval=0x%x before writing 0xffffffff's \n", ((ix/4)-4), testval);

      /* Write all f's and read back value */

      pciConfigOutLong(pciBusNo, pciDevNo, pciFuncNo, ix, 0xffffffff);
      pciConfigInLong(pciBusNo, pciDevNo, pciFuncNo, ix, &testval);
      
      	if(!BAR_IS_IMPLEMENTED(testval)) {
        	printf("BAR %d not implemented\n", ((ix/4)-4));
	} else {
		if(BAR_IS_MEM_ADDRESS_DECODER(testval)) {
			printf("BAR %d is a Memory Address Decoder\n", ((ix/4)-4));
			printf("Configuring BAR %d for address 0x%x\n", ix, BTVID_MMIO_ADDR);
        		pciConfigOutLong(pciBusNo, pciDevNo, pciFuncNo, ix, BTVID_MMIO_ADDR);
			printf("BAR configured \n");
			
			if(BAR_IS_32_BIT_DECODER(testval))
				printf("BAR %d is a 32-Bit Decoder \n", ((ix/4)-4));
			else if(BAR_IS_64_BIT_DECODER(testval))	
				printf("BAR %d is a 64-Bit Decoder \n", ((ix/4)-4));
			else
				printf("BAR %d memory width is undefined \n", ((ix/4)-4));

			if(BAR_IS_PREFETCHABLE(testval))
				printf("BAR %d address space is prefetachable \n", ((ix/4)-4));
			
		} else if(BAR_IS_IO_ADDRESS_DECODER(testval)) {
			printf("BAR %d is an IO Address Decoder \n", ((ix/4)-4));
		} else {
			printf("BAR %d is niether an IO Address Decoder or an Memory Address Decoder (error probably) \n", ((ix/4)-4));	
		}
		
	printf("BAR %d decodes a space 2^%i big\n", ((ix/4)-4), 
		baseAddressRegisterSizeOfDecodeSpace(testval));
	}

	printf("\n\n");
  }

  /* Set the INTA vector */
  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, &irq);
  printf("Found Bt878 configured for IRQ line: %d\n", irq);
  irq = BT878INT;
  pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, irq);
  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, &irq);
  printf("Updated Bt878 IRQ line to: 0x%x\n", irq);

  /* Configure Cache Line Size Register -- Write-Command 

     Do not use cache line.

   */
  pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_CACHE_LINE_SIZE, 0x0);

  /* Configure Latency Timer */
  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, &byte);
  printf("Bt878 Allowable PCI bus latency = 0x%x\n", byte);
  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_MIN_GRANT, &byte);
  printf("Bt878 PCI bus min grant = 0x%x\n", byte);
  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_MAX_LATENCY, &byte);
  printf("Bt878 PCI bus max latency = 0x%x\n", byte);

  pciConfigOutByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, 0xFF);

  pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_LATENCY_TIMER, &byte);
  printf("Modified Bt878 Allowable PCI bus latency = 0x%x\n", byte);


  /* Enable the device's capabilities as specified */
  pciConfigOutWord(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, (unsigned short) command);
  
}

/* This function takes the entire 32 bit readback register value including bits 
 * [3:0] and returns the position starting from 0 of the first bit not 0*/

int baseAddressRegisterSizeOfDecodeSpace(int returnval) {

	int tmp = 0;
	int bitpos = 0;
	int i = 0;
	
	tmp = returnval;
       	t