btvid2.c

developed under vxwork, support bt878 video card, use socket to stream video out.

  printf("Brightness was %d\n", bright);

  if(b > 255)
    b = 255;
  else if(b < 0)
    b = 0;

  bright = b + 0x80;

  if(bright > 0xFF)
    bright = bright - 0xFF;

  hb = bright;

  PCI_WRITE(BRIGHTNESS_REG,0x0,hb);

}


void set_contrast(int c)
{
  int contrast;
  unsigned int hc;

  PCI_READ(CONTRAST_REG,0x0,&hc);

  if(hc < 0x7f)
    contrast = hc + 0x80;
  else
    contrast = hc - 0x7f;

  printf("Contrast was %d\n", contrast);

  if(c > 255)
    c = 255;
  else if(c < 0)
    c = 0;

  contrast = c + 0x80;

  if(contrast > 0xFF)
    contrast = contrast - 0xFF;

  hc = contrast;

  PCI_WRITE(CONTRAST_REG,0x0,hc);

}


void vdfc_capture(void)
{
  /* Set the video capture control -- ODD and EVEN through VFDC */
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x00000013);
}


void vbi_capture(void)
{

  /* Set the video capture control -- ODD and EVEN VBI 

     Given NTSC full resolution frame format of:

      9   VSYNC           1          9
     11   VBI            10         20    -- Vertical Blanking Interval
    242.5 ODD            21        263.5
      9   VSYNC         263.5      272.5
     11   VBI           272.5      283.5  -- Vertical Blanking Interval
    242.5 EVEN          283.5      525
    -------------------------------------
    525

    
   */

  /**** Enable VBI Capture ****/
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x0000001C);

 
  /**** Standard VBI ****/ 
  PCI_WRITE(VBI_PACKET_SIZE_LO_REG,0x0,0x0000000B);
  PCI_WRITE(VBI_PACKET_SIZE_HI_REG,0x0,0x00000000);

}


void load_test_mc(int mc)
{
  if(mc == TEST_MICROCODE)
  {
    initialize_test_mc();
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_test_microcode[0]));
  }
  else
  {
    printf("Bad test MC\n");
  }
}


void load_frame_mc(int fsize)
{
  initialize_frame_mc(fsize);

  if((fsize==NTSC_320_X_240) || (fsize==NTSC_320_X_240_GS))
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_microcode[0]));
  else if(fsize==NTSC_80_X_60)
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_puny_microcode[0]));
  else if(fsize==NTSC_640_X_480)
    PCI_WRITE(DMA_RISC_START_ADDR_REG,0x0,(unsigned int)&(dma_large_microcode[0]));
}


void sw_reset(void)
{
  PCI_WRITE(RESET_REG,0x0,0x00000001);
}


void toggle_fifo(int t)
{
  unsigned int testval;

  PCI_READ(DMA_CTL_REG,0x0,&testval);

  if(t)
  {
    /* Enable FIFO */
    testval = testval | 0x00000001;
  }
  else
  {
    /* Disable FIFO */
    testval = testval & 0xFFFFFFFE;
  }

  PCI_WRITE(DMA_CTL_REG,0x0,testval);
}


void toggle_dma(int t)
{
  unsigned int testval;

  PCI_READ(DMA_CTL_REG,0x0,&testval);

  if(t)
  {
    /* Enable DMA */
    testval = testval | 0x00000002;
  }
  else
  {
    /* Disable DMA */
    testval = testval & 0xFFFFFFFD;
  }

  PCI_WRITE(DMA_CTL_REG,0x0,testval);

}


void start_acq(void)
{
  /* Enable DMA and data FIFO 

     The packed trigger point is set to max.

   */
  PCI_WRITE(DMA_CTL_REG,0x0,0x0000000F);
}


void halt_acq(void)
{
  /* Disable DMA and data FIFO */
  PCI_WRITE(DMA_CTL_REG,0x0,0x00000000);
}


void report(void)
{
  logMsg("\n\n******** Frame = %d ********\n", frame_acq_cnt,0,0,0,0,0);
  intel_pci_status();
  test_status();
  logMsg("******** Error Status:\n",0,0,0,0,0,0);
  logMsg("last_dstatus = 0x%x\n", last_dstatus,0,0,0,0,0);
  logMsg("last_isr_status = 0x%x\n", last_isr_status,0,0,0,0,0);
  logMsg("total_dma_disabled_errs = %d\n", total_dma_disabled_errs,0,0,0,0,0);
  logMsg("total_sync_errs = %d\n", total_sync_errs,0,0,0,0,0);
  logMsg("total_abort_errs = %d\n", total_abort_errs,0,0,0,0,0);
  logMsg("total_dma_errs = %d\n", total_dma_errs,0,0,0,0,0);
  logMsg("total_parity_errs = %d\n", total_parity_errs,0,0,0,0,0);
  logMsg("total_bus_parity_errs = %d\n", total_bus_parity_errs,0,0,0,0,0);
  logMsg("total_fifo_overrun_errs = %d\n", total_fifo_overrun_errs,0,0,0,0,0);
  logMsg("total_fifo_resync_errs = %d\n", total_fifo_resync_errs,0,0,0,0,0);
  logMsg("total_bus_latency_errs = %d\n", total_bus_latency_errs,0,0,0,0,0);
  logMsg("total_risc_ints = %d\n", total_risc_ints,0,0,0,0,0);
  logMsg("total_ints = %d\n", total_ints,0,0,0,0,0);
  logMsg("total_write_tags = %d\n", total_write_tags,0,0,0,0,0);
  logMsg("total_skip_tags = %d\n", total_skip_tags,0,0,0,0,0);
  logMsg("total_jump_tags = %d\n", total_jump_tags,0,0,0,0,0);
  logMsg("total_sync_tags = %d\n", total_sync_tags,0,0,0,0,0);
  logMsg("******** Frame = %d ********\n", frame_acq_cnt,0,0,0,0,0);

}


void pci_inta_isr(int param)
{

  /*logMsg("Int!\n",0,0,0,0,0,0);*/

  total_ints++;
  wvEvent((total_ints % 999)+1000,NULL,0);


  PCI_READ(INT_STATUS_REG,0x0,&last_isr_status);

  /* Clear the INTA interrupt status 

     Clear ALL RR bits:
     PCI_WRITE(INT_STATUS_REG,0x0,0x000FFB3F);

   */
  PCI_WRITE(INT_STATUS_REG,0x0,last_isr_status);


  if(last_isr_status & int_errors_to_check)
  {

    /* Did error halt the DMA? */
    if(last_isr_status & 0x08000000)
      total_dma_disabled_errs++;

    halt_acq();

    start_acq();


    if(last_isr_status & SCERR_INT)
    {
      total_sync_errs++;
      halt_acq();
      start_acq();
    }

    if(last_isr_status & OCERR_INT)
    {
      total_dma_errs++;
      halt_acq();
      start_acq();
    }

    if(last_isr_status & PABORT_INT)
      total_abort_errs++;

    if(last_isr_status & RIPERR_INT)
      total_parity_errs++;

    if(last_isr_status & PPERR_INT)
      total_bus_parity_errs++;

    if(last_isr_status & FDSR_INT)
      total_fifo_resync_errs++;

    if(last_isr_status & FTRGT_INT)
      total_fifo_overrun_errs++;

    if(last_isr_status & FBUS_INT)
      total_bus_latency_errs++;

  }

  
  else if(last_isr_status & RISCI_INT)
  {
    total_risc_ints++;

    if(last_isr_status & (DMA_MC_WRITE<<12))
      total_write_tags++;

    if(last_isr_status & (DMA_MC_SKIP<<12))
      total_skip_tags++;

    if(last_isr_status & (DMA_MC_JUMP<<12))
      total_jump_tags++;

    if(last_isr_status & (DMA_MC_SYNC<<12))
      total_sync_tags++;

    /* Bump the frame_acq_cnt */
    frame_acq_cnt++;

    current_frame = !current_frame;

    /* Notify client that frame is ready */
    semGive(frameRdy);

    /* Check the device status */
    PCI_READ(BTVID_MMIO_ADDR,0x0,&last_dstatus);
  }


}


void full_reset(void)
{

  halt_acq();

  disable_capture();

  taskDelete(btvid_tid);

  frame_acq_cnt = 0;
  frame_rdy_cnt = 0;
  last_dstatus = 0x0;
  last_isr_status = 0x0;
  total_dma_disabled_errs = 0x0;
  total_sync_errs = 0x0;
  total_abort_errs = 0x0;
  total_dma_errs = 0x0;
  total_parity_errs = 0x0;
  total_bus_parity_errs = 0x0;
  total_fifo_overrun_errs = 0x0;
  total_fifo_resync_errs = 0x0;
  total_bus_latency_errs = 0x0;
  total_risc_ints = 0x0;
  total_write_tags = 0x0;
  total_skip_tags = 0x0;
  total_jump_tags = 0x0;
  total_sync_tags = 0x0;

  semDelete(frameRdy);

  sw_reset();

  intel_pci_clear_status();

  reset_status();

}



void activate(int fsize)
{
  test_status();

  connect_pci_int(BT878INT);

  sysIntEnablePIC(BT878INT);

  configure_ntsc(fsize);
  logMsg("Configured NTSC\n",0,0,0,0,0,0);

  set_mux(1);
  logMsg("Set mux\n",0,0,0,0,0,0);

  load_frame_mc(fsize);
  printf("Loaded MC\n");
  clear_buffers(fsize);
  enable_capture();
  start_acq();

  test_status();
}


void activate_test(int mc)
{
  test_status();

  connect_pci_int(BT878INT);
  sysIntEnablePIC(BT878INT);

  configure_ntsc(1);

  set_mux(1);

  load_test_mc(mc);
  clear_buffers(2);
  enable_capture();
  start_acq();


  test_status();
}


void connect_pci_int(int inum)
{

  pciIntConnect((INUM_TO_IVEC (inum+INT_NUM_IRQ0)), (VOIDFUNCPTR)pci_inta_isr, 0);

}


void processRGBFrame(char *buffbyteptr)
{
    int idx, idx2;
    char *savebuffbyteptr = buffbyteptr;

    for(idx=0;idx<76800;idx++)
    {
        idx2 = idx * 3;

        rgb_buffer[idx2] = (unsigned char)*(savebuffbyteptr+2);
        rgb_buffer[idx2+1] = (unsigned char)*(savebuffbyteptr+1);
        rgb_buffer[idx2+2] = (unsigned char)*(savebuffbyteptr);
        savebuffbyteptr+=4;

    }
}



void btvid_drvr(void)
{
  int idx;
  int idx2;
  mqd_t mymq;
  int prio;
  int nbytes;
  char *savebuffbyteptr = (char *)&(save_buffer[0]);
  frameRdy = semBCreate(SEM_Q_FIFO, SEM_EMPTY);
  streamRdy = semBCreate(SEM_Q_FIFO, SEM_EMPTY);

  /* setup common message q attributes */
  mq_attr.mq_maxmsg = 4;
  mq_attr.mq_msgsize = MAX_MSG_SIZE;

  mq_attr.mq_flags = 0;


  /* note that VxWorks does not deal with permissions? */
  mymq = mq_open(SNDRCV_MQ, O_CREAT|O_RDWR, 0, &mq_attr);

  if(mymq == (mqd_t)ERROR)
    perror("mq_open");



  /******** Initialization and Test ********/
  intel_pci_config();
  btvid_controller_config();
  test_dstatus();
  test_status();


  /******** Main LOOP ********/
  while(1)
  {

    /* Await a activate command here */
    semTake(frameRdy, WAIT_FOREVER);

    frame_rdy_cnt++;
    
    if((acq_type == NTSC_320_X_240) && ((frame_acq_cnt % frameProcRate)==0))
    {

      frameProcCnt++;

      wvEvent((frameProcCnt % 999)+2000,NULL,0);

      savebuffbyteptr = (char *)&(frame_buffer[current_frame][0]);

      
      processRGBFrame(savebuffbyteptr);

      if(start_frame_tx && enable_streaming && ((frame_acq_cnt % frameProcRate)==0))
      {
         /* semGive(streamRdy); */

         /* send message with priority=30 */
         if((nbytes = mq_send(mymq, (char *)frame_acq_cnt, sizeof(frame_acq_cnt), 30)) == ERROR)
         {
           perror("mq_send");
         }

         
         wvEvent((frameProcCnt % 999)+3000,NULL,0);
      }

    } /* end if NTSC to process */

  } /* end while forever */

}


void start_video(void)
{

	char temp;
	int pciBusNo = PCI_DEV[CAPTURE_VIDEO_CARD].busNo;
  	int pciDevNo = PCI_DEV[CAPTURE_VIDEO_CARD].deviceNo;
  	int pciFuncNo = PCI_DEV[CAPTURE_VIDEO_CARD].funcNo;

	/* In order to see logmsg's you need to add stdout's file handle (1) */
	logFdAdd(1);
	initializePCI_DEV();
	pciConfigInByte(pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_DEV_INT_LINE, &temp);
	BT878INT = (int) temp;
	btvid_tid = taskSpawn("tBtvid", 10, 0, (1024*8), (FUNCPTR) btvid_drvr, 0,0,0,0,0,0,0,0,0,0);