btvid2.c

developed under vxwork, support bt878 video card, use socket to stream video out.

          dma_puny_microcode[mcidx+j] = DMA_MC_SKIP_40_SOL;
          dma_puny_microcode[mcidx+j+1] = DMA_MC_SKIP_40_EOL;
        }
        else
        {
          dma_puny_microcode[mcidx+j] = DMA_MC_WRITE_80_LINE;
          dma_puny_microcode[mcidx+j+1] = (unsigned int)&(puny_frame_buffer[i][(20+(k*40))]);
        }
 
      }

      j=32;

      /* VRE FIELD SYNC */ 
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_VRE_WORD_0; j++;
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 30 lines of EVEN microcode */
      for(j=36,k=0;j<66;j+=2,k++)
      {

        /* even line */
        if(replace_write_with_skip)
        {
          dma_puny_microcode[mcidx+j] = DMA_MC_SKIP_40_SOL;
          dma_puny_microcode[mcidx+j+1] = DMA_MC_SKIP_40_EOL;
        }
        else
        {
          dma_microcode[mcidx+j] = DMA_MC_WRITE_80_LINE;
          dma_microcode[mcidx+j+1] = (unsigned int)&(puny_frame_buffer[i][0+(k*40)]);
        }
      }
 
      j = 66;
   
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_VRO_WORD_0_IRQ; j++;
      dma_puny_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

    }

    dma_puny_microcode[(NUMFRAMES*PUNYMCSIZE)] = DMA_MC_JUMP_TO_BEG;
    dma_puny_microcode[(NUMFRAMES*PUNYMCSIZE)+1] = (unsigned int)&(dma_microcode[0]);

  }

  else if(fsize==NTSC_320_X_240_GS)
  {
    /* For NUMFRAMES Frames */
    for(i=0;i<NUMFRAMES;i++)
    {

      mcidx = MCSIZE * i; j = 0;

      /* FIELD SYNC */  
      dma_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 120 lines of ODD microcode */
      for(j=2,k=0;j<242;j+=2,k++)
      {
  
        /* odd line */
        if(replace_write_with_skip)
        {
          dma_microcode[mcidx+j] = DMA_MC_SKIP_40_SOL;
          dma_microcode[mcidx+j+1] = DMA_MC_SKIP_40_EOL;
        }
        else
        {
          dma_microcode[mcidx+j] = DMA_MC_WRITE_80_LINE;
          dma_microcode[mcidx+j+1] = (unsigned int)&(y8_frame_buffer[i][(80+(k*160))]);
        }
 
      }

      j=242;

      /* VRE FIELD SYNC */ 
      dma_microcode[mcidx+j] = DMA_MC_SYNC_VRE_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 120 lines of EVEN microcode */
      for(j=246,k=0;j<486;j+=2,k++)
      {

        /* even line */
        if(replace_write_with_skip)
        {
          dma_microcode[mcidx+j] = DMA_MC_SKIP_40_SOL;
          dma_microcode[mcidx+j+1] = DMA_MC_SKIP_40_EOL;
        }
        else
        {
          dma_microcode[mcidx+j] = DMA_MC_WRITE_80_LINE;
          dma_microcode[mcidx+j+1] = (unsigned int)&(y8_frame_buffer[i][0+(k*160)]);
        }
      }
 
      j = 486;
   
      dma_microcode[mcidx+j] = DMA_MC_SYNC_VRO_WORD_0_IRQ; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

    }

    dma_microcode[(NUMFRAMES*MCSIZE)] = DMA_MC_JUMP_TO_BEG;
    dma_microcode[(NUMFRAMES*MCSIZE)+1] = (unsigned int)&(dma_microcode[0]);

  }

    /* For NUMFRAMES Frames */
  else if(fsize==NTSC_320_X_240)
  {
    /* For NUMFRAMES Frames */
    for(i=0;i<NUMFRAMES;i++)
    {

      mcidx = MCSIZE * i; j = 0;

      /* FIELD SYNC */  
      dma_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 120 lines of ODD microcode */
      for(j=2,k=0;j<242;j+=2,k++)
      {
  
        /* odd line */
        if(replace_write_with_skip)
        {
          dma_microcode[mcidx+j] = DMA_MC_SKIP_640_SOL;
          dma_microcode[mcidx+j+1] = DMA_MC_SKIP_640_EOL;
        }
        else
        {
          dma_microcode[mcidx+j] = DMA_MC_WRITE_1280_LINE;
          dma_microcode[mcidx+j+1] = (unsigned int)&(frame_buffer[i][(320+(k*640))]);
        }
 
      }

      j=242;

      /* VRE FIELD SYNC */ 
      dma_microcode[mcidx+j] = DMA_MC_SYNC_VRE_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 120 lines of EVEN microcode */
      for(j=246,k=0;j<486;j+=2,k++)
      {

        /* even line */
        if(replace_write_with_skip)
        {
          dma_microcode[mcidx+j] = DMA_MC_SKIP_640_SOL;
          dma_microcode[mcidx+j+1] = DMA_MC_SKIP_640_EOL;
        }
        else
        {
          dma_microcode[mcidx+j] = DMA_MC_WRITE_1280_LINE;
          dma_microcode[mcidx+j+1] = (unsigned int)&(frame_buffer[i][0+(k*640)]);
        }
      }
 
      j = 486;
   
      dma_microcode[mcidx+j] = DMA_MC_SYNC_VRO_WORD_0_IRQ; j++;
      dma_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

    }

    dma_microcode[(NUMFRAMES*MCSIZE)] = DMA_MC_JUMP_TO_BEG;
    dma_microcode[(NUMFRAMES*MCSIZE)+1] = (unsigned int)&(dma_microcode[0]);

  }

  else if(fsize==NTSC_640_X_480)
  {
    /* For NUMFRAMES Frames */
    for(i=0;i<NUMFRAMES;i++)
    {

      mcidx = LGMCSIZE * i; j = 0;

      /* FIELD SYNC */  
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 240 lines of ODD microcode */
      for(j=2,k=0;j<482;j+=2,k++)
      {

        /* odd line */
        dma_microcode[mcidx+j] = DMA_MC_SKIP_1280_SOL;
        dma_microcode[mcidx+j+1] = DMA_MC_SKIP_1280_EOL;
      }

      j=482;

      /* VRE FIELD SYNC */ 
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_VRE_WORD_0; j++;
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_FM1_WORD_0; j++;
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

      /* Initialize 240 lines of EVEN microcode */
      for(j=486;j<966;j+=2)
      {

        /* even line */
        dma_microcode[mcidx+j] = DMA_MC_SKIP_1280_SOL;
        dma_microcode[mcidx+j+1] = DMA_MC_SKIP_1280_EOL;
      }
 
      j = 966;
   
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_VRO_WORD_0_IRQ; j++;
      dma_large_microcode[mcidx+j] = DMA_MC_SYNC_WORD_1; j++;

    } /* end for NUMFRAMES */

    dma_large_microcode[(NUMFRAMES*LGMCSIZE)] = DMA_MC_JUMP_TO_BEG;
    dma_large_microcode[(NUMFRAMES*LGMCSIZE)+1] = (unsigned int)&(dma_microcode[0]);

  } /* end else 640x480 */

}



int configure_ntsc(int fsize)
{
  unsigned int testval = 0;


  /* Software Reset */
  PCI_WRITE(RESET_REG,0x0,0x00000001);


  /* Set the oscillator frequency for NTSC 

     0x00000020 = xtal 0 input
     0x00000000 = CLKx1

  */
  PCI_READ(TIMING_GEN_REG,0x0,&testval);
  printf("Timing Gen Ctl Reg = 0x%x\n", testval);

  PCI_WRITE(TIMING_GEN_REG,0x0,0x00000000);


  if((fsize==NTSC_320_X_240))
  {
    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 323

      Crop 2 on left, 1 on right for 320 pixels / line

      For 320x240, want:

      MSB_CROP= 0x0000011

      Hactive=  0x00000140 (320)   Vactive= 0x000001e0 (480)
      Hdelay=   0x0000003c (60)    Vdelay=  0x00000016 (22)
      Hscale=   0x00001555         Vscale=  0x00007e00

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000011);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0,0x00000011);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x00000040);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x00000040);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x0000003C);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x0000003C);

    /* Set HSCALE for 320 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x00000055);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x00000055);

    /* Set VSCALE for 240 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);

    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000000);
    acq_type = NTSC_320_X_240;

  }

  if((fsize==NTSC_320_X_240_GS))
  {
    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 323

      Crop 2 on left, 1 on right for 320 pixels / line

      For 320x240, want:

      MSB_CROP= 0x0000011

      Hactive=  0x00000140 (320)   Vactive= 0x000001e0 (480)
      Hdelay=   0x0000003c (60)    Vdelay=  0x00000016 (22)
      Hscale=   0x00001555         Vscale=  0x00007e00

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000011);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0,0x00000011);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x0000002C);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x0000002C);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000046);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000046);

    /* Set HSCALE for 320 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000015);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x00000055);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x00000055);

    /* Set VSCALE for 240 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x0000007E);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);

    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000066);
    acq_type = NTSC_320_X_240_GS;
  }

  else if(fsize==NTSC_80_X_60)
  {
    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 81

      Crop 0.79 on left for 80 pixels / line

      For 80X60, want:

      MSB_CROP= 0x0000000

      Hactive=  0x00000050 (80)   Vactive=  0x000001e0 (480)
      Hdelay=   0x00000010 (16)    Vdelay=  0x00000016 (22)
      Hscale=   0x0000861A         Vscale=  0x00007200

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000010);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0, 0x00000010);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x00000050);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x00000050);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000010);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000010);

    /* Set HSCALE for 320 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000086);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000086);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x0000001A);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x0000001A);

    /* Set VSCALE for 240 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x00000072);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x00000072);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);

    /* Set color format for Y8 GRAYSCALE on ODD and EVEN */
    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000066);

  }

  else if(fsize==NTSC_640_X_480)
  {


    /*

      Set up the delay and active registers so that they cover
      full resolution.

      Scaled pixels / line = 646

      Crop 4 on left, 2 on right for 640 pixels / line

      For 640x480, want:

      MSB_CROP= 0x0000012

      Hactive= 0x00000280 (640)    Vactive= 0x000001e0 (480)
      Hdelay=  0x00000078 (120)    Vdelay=  0x00000016 (22)
      Hscale=  0x000002aa          Vscale=  0x00006000

    */

    PCI_WRITE(MSB_CROP_EVEN_REG,0x0,0x00000012);
    PCI_WRITE(MSB_CROP_ODD_REG,0x0,0x00000012);

    PCI_WRITE(HACTIVE_LO_EVEN_REG,0x0,0x00000080);
    PCI_WRITE(HACTIVE_LO_ODD_REG,0x0,0x00000080);
    PCI_WRITE(VACTIVE_LO_EVEN_REG,0x0,0x000000E0);
    PCI_WRITE(VACTIVE_LO_ODD_REG,0x0,0x000000E0);
    PCI_WRITE(VDELAY_LO_EVEN_REG,0x0,0x00000016);
    PCI_WRITE(VDELAY_LO_ODD_REG,0x0,0x00000016);
    PCI_WRITE(HDELAY_LO_EVEN_REG,0x0,0x00000078);
    PCI_WRITE(HDELAY_LO_ODD_REG,0x0,0x00000078);

    /* Set HSCALE for 640 pixels per line */
    PCI_WRITE(HSCALE_EVEN_MSB_REG,0x0,0x00000002);
    PCI_WRITE(HSCALE_ODD_MSB_REG,0x0,0x00000002);
    PCI_WRITE(HSCALE_EVEN_LSB_REG,0x0,0x000000AA);
    PCI_WRITE(HSCALE_ODD_LSB_REG,0x0,0x000000AA);

    /* Set VSCALE for 480 lines per frame */
    PCI_WRITE(VSCALE_EVEN_MSB_REG,0x0,0x00000060);
    PCI_WRITE(VSCALE_ODD_MSB_REG,0x0,0x00000060);
    PCI_WRITE(VSCALE_EVEN_LSB_REG,0x0,0x00000000);
    PCI_WRITE(VSCALE_ODD_LSB_REG,0x0,0x00000000);


    /* Set color format for RGB32 on ODD and EVEN */
    PCI_WRITE(COLOR_FORMAT_REG,0x0,0x00000000);
  }

  /* Enable the DMA RISC instruction IRQ */ 
  PCI_WRITE(INT_ENABLE_REG,0x0,(int_errors_to_check|RISCI_INT|VPRES_INT));

  /* Reduce frame rate from max of 30 frames/sec or 60 fields/sec */
  PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* reset */
  PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* set */

}


int decimate_frames(int count)
{
  unsigned int fcnt = count;

  if(count > 60 || count < 0)
    return -1;

  else
  {
    /* Reduce frame rate from max of 30 frames/sec */
    PCI_WRITE(TEMP_DECIMATION_REG,0x0,0x00000000);  /* reset */
    PCI_WRITE(TEMP_DECIMATION_REG,0x0,fcnt);  /* set */

    return count;
  }

}


void disable_capture(void)
{
  PCI_WRITE(CAPTURE_CTL_REG,0x0,0x00000000);
}


void enable_capture(void)
{
  vdfc_capture();
}


void set_brightness(int b)
{
  int bright;
  unsigned int hb;

  PCI_READ(BRIGHTNESS_REG,0x0,&hb);

  if(hb < 0x7f)
    bright = hb + 0x80;
  else
    bright = hb - 0x7f;