generic_ram_2.vhd

一个电驴上下的51的CORE

-- Standard RAM with input and output Data Bus
-- December 2000
--
-- Arnaud DEPAIGNE
-- Nicolas JOURDAN
-- Ecole polytechnique de l'Universite de Nantes
-- 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

entity RamChip is
	generic(Data_Size: integer := 8;
		Bus_Size: integer := 4);
	
	port (RST : in std_logic;
	      Address	: in unsigned(Bus_Size-1 downto 0);
              InData	: in unsigned(Data_Size-1 downto 0);
              OutData   : out unsigned(Data_Size-1 downto 0);
              CS, WE, OE: in std_logic);
end RamChip;

architecture Behaviour of RamChip is
	    subtype Word is unsigned(Data_size-1 downto 0);
	    type MemType is array (0 to (2**Bus_Size)-1) of Word;
	    signal Memory: MemType;
begin
	
    	process(RST,CS)
	begin
		if( RST = '1' ) then
			for i in 0 to (2**Bus_Size)-1 loop
				Memory <= (others => Word'(others=>'-'));            
			end loop;
			OutData <= Word'(others=>'Z');
		elsif(CS = '0') then
			if (conv_integer(Address) < (2**Bus_Size)) then
      				if OE = '1' then                  -- Read operation
        				OutData <= Memory(conv_integer(Address));
	      			elsif WE = '1' then               -- Write operation
	        			Memory(conv_integer(Address)) <= InData;
	      			end if;
	      		end if;
		end if;
  	end process;
end;

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.STD_LOGIC_ARITH.all;

-- *****************************************
-- *              ADDRESS DECODER
-- *****************************************

entity Add_decoder is 
	generic(Decod_Size: integer := 8);
	
       	port(a: in unsigned(Decod_Size-1 downto 0); 
       	     s: out unsigned((2**Decod_Size)-1 downto 0);
	     n: inout integer);
end Add_decoder;

architecture Structural of Add_decoder is 
begin 
	process(a)
		variable int_a: integer; -- range 0 to (2**Decod_Size)-1
		variable test: std_logic;
	begin 

		test := '1';

		for j in 0 to Decod_Size-1 loop
			if not(a(j) = '1') and not(a(j) = '0') then
				test := '0';
				n <= n mod (2**Decod_Size); -- initialisation
			end if;
            	end loop;

		for i in 0 to (2**Decod_Size)-1 loop
			s(i) <= '1';
        	end loop;
            	
            	if (test = '1') then
            		n <= conv_integer(a);
            		s(conv_integer(a)) <= '0';
		end if;            		
            	
	end process; 	
end Structural;

-- *****************************************
-- *              GENERIC_RAM STRUCTURE 
-- *****************************************

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.STD_LOGIC_ARITH.all;

entity GENERIC_RAM_2 is
	generic(Data_Ram: integer := 8;
		Addr_Ram: integer := 8;
		Bus_Size_Unit : integer := 4);

	port (	RST : in std_logic;
		abus: in unsigned(Addr_Ram-1 downto 0);
	      	indbus: in unsigned(Data_Ram-1 downto 0);
	      	outdbus: out unsigned(Data_Ram-1 downto 0);
              	WE, OE : in std_logic);
end GENERIC_RAM_2; 

architecture Structural of GENERIC_RAM_2 is

	component RamChip
		generic(Data_Size: integer := 8;
			Bus_size: integer := 4);

		port (RST : in std_logic;
		      Address	: in unsigned(Bus_Size-1 downto 0);
	              InData	: in unsigned(Data_Size-1 downto 0);
	              OutData   : out unsigned(Data_Size-1 downto 0);
	              CS, WE, OE: in std_logic);			      
	end component;

	component Add_decoder
		generic(Decod_Size: integer := 4);
		
		port(a: in unsigned (Decod_Size downto 0); 
       	     	     s: out unsigned((2**Decod_Size)-1 downto 0);
       	     	     n: inout integer);
	end component;

	subtype Word is unsigned(Data_Ram-1 downto 0);
	type TypeBus is array (0 to (2**(Addr_Ram-Bus_Size_Unit))-1) of Word;
	signal All_Int_Data_Bus : TypeBus;
	
	signal CSI: unsigned((2**(Addr_Ram-Bus_Size_Unit))-1 downto 0);
	signal nobus: integer;
begin

	rams : for i in 0 to (2**(Addr_Ram-Bus_Size_Unit))-1 generate
		ram : RamChip generic map(Data_Ram, Bus_Size_Unit) port map (RST, abus(Bus_Size_Unit-1 downto 0), indbus, All_Int_Data_Bus(i), CSI(i), WE, OE);
	end generate rams;

	dec : Add_decoder generic map(Addr_Ram-Bus_Size_Unit) port map(abus(Addr_Ram-1 downto Bus_Size_Unit), CSI, nobus);

	with RST select
		outdbus <= Word'(others=>'Z') when '1',
			   All_Int_Data_Bus(nobus) when '0',
			   Word'(others=>'Z') when others;
end Structural;