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来自「verilog 写的 memory controller」· 代码 · 共 44 行

#!/bin/csh
#
# simulation script for memory controller testbench
# (C) 2002 Richard Herveille
#          [e-mail]
#
set mem_ctrl = ../../../..
set bench    = $mem_ctrl/bench/richard

ncverilog							\
								\
	+access+rwc +linedebug					\
#	+define+WAVES						\
								\
	+incdir+$bench/verilog					\
								\
	+libext+.v						\
	-y $SYNOPSYS/dw/sim_ver/				\
								\
								\
	$mem_ctrl/rtl/verilog/mc_adr_sel.v			\
	$mem_ctrl/rtl/verilog/mc_cs_rf.v			\
	$mem_ctrl/rtl/verilog/mc_dp.v				\
	$mem_ctrl/rtl/verilog/mc_incn_r.v			\
	$mem_ctrl/rtl/verilog/mc_mem_if.v			\
	$mem_ctrl/rtl/verilog/mc_obct.v				\
	$mem_ctrl/rtl/verilog/mc_obct_top.v			\
	$mem_ctrl/rtl/verilog/mc_rd_fifo.v			\
	$mem_ctrl/rtl/verilog/mc_refresh.v			\
	$mem_ctrl/rtl/verilog/mc_rf.v				\
	$mem_ctrl/rtl/verilog/mc_timing.v			\
	$mem_ctrl/rtl/verilog/mc_wb_if.v			\
	$mem_ctrl/rtl/verilog/mc_top.v				\
								\
	$bench/verilog/models/m8kx8.v				\
	$bench/verilog/models/mt48lc16m16a2.v			\
	$bench/verilog/models/mt58l1my18d.v			\
	$bench/verilog/wb_master_model.v			\
	$bench/verilog/checkers.v				\
	$bench/verilog/bench.v					\