c8051_tb.v

c8051 core 不是源代码版的

//-----------------------------------------------------------------------
//
// Copyright (c) 1999 CAST, Inc.
//
//-----------------------------------------------------------------------
//
//  C8051 Sample Verilog Testbench
//
//-----------------------------------------------------------------------

`timescale 1 ns / 1 ns // timescale for following modules
`define false 1'b 0
`define true 1'b 1

module C8051_tb ;

reg     rst; 
reg     clk; 
reg     ea; 
reg     [7:0] p0_in; 
reg     [7:0] p1_in; 
reg     [7:0] p2_in; 
reg     [7:0] p3_in; 
reg     [7:0] databus_rom; 
reg     [7:0] databus_ram; 

wire    [7:0] databus_out; 
wire    [7:0] p0_out; 
wire    [7:0] p1_out; 
wire    [7:0] p2_out; 
wire    [7:0] p3_out; 
wire    ale; 
wire    psen; 
wire    [11:0] rom_addr; 
wire    rom_oe; 
wire    [7:0] ram_addr; 
wire    ram_we; 
wire    ram_oe; 

reg     comparator_failure; 
reg     [50:0] stm[0:8000];	// stores stimulus
reg     [63:0] cmp[0:3999];	// stores expected results 
integer stm_index;
integer cmp_index;

// Expected results 
reg    rst_VAR;
reg    clk_VAR;
reg    ea_VAR;
reg    [7:0]  p0_in_VAR;
reg    [7:0]  p1_in_VAR;
reg    [7:0]  p2_in_VAR;
reg    [7:0]  p3_in_VAR;
reg    [7:0]  databus_rom_VAR;
reg    [7:0]  databus_ram_VAR;
reg    [7:0]  databus_out_VAR; 
reg    [7:0]  p0_out_VAR; 
reg    [7:0]  p1_out_VAR; 
reg    [7:0]  p2_out_VAR; 
reg    [7:0]  p3_out_VAR; 
reg    ale_VAR; 
reg    psen_VAR; 
reg    [11:0]  rom_addr_VAR; 
reg    rom_oe_VAR; 
reg    [7:0]  ram_addr_VAR; 
reg    ram_we_VAR; 

initial 
   begin
      comparator_failure = `false;	
      $readmemb("C8051.stm", stm);
      $readmemb("C8051.cmp", cmp);
      stm_index = 0;
      cmp_index = 0;
   end

C8051 model (.rst(rst),
             .clk(clk),
             .ea(ea),
             .p0_in(p0_in),
             .p1_in(p1_in),
             .p2_in(p2_in),
             .p3_in(p3_in),
             .databus_rom(databus_rom),
             .databus_ram(databus_ram),
             .databus_out(databus_out),
             .p0_out(p0_out),
             .p1_out(p1_out),
             .p2_out(p2_out),
             .p3_out(p3_out),
             .ale(ale),
             .psen(psen),
             .rom_addr(rom_addr),
             .rom_oe(rom_oe),
             .ram_addr(ram_addr),
             .ram_we(ram_we),
             .ram_oe(ram_oe));

always 
   begin
      if (stm_index != 8000) 
         begin
            #10;
            {rst_VAR, clk_VAR, ea_VAR, p0_in_VAR, p1_in_VAR, p2_in_VAR, p3_in_VAR, databus_rom_VAR, databus_ram_VAR} = stm[stm_index];
            rst = rst_VAR;	
            clk = clk_VAR;	
            ea = ea_VAR;	
            p0_in = p0_in_VAR;	
            p1_in = p1_in_VAR;	
            p2_in = p2_in_VAR;	
            p3_in = p3_in_VAR;	
            databus_rom = databus_rom_VAR;	
            databus_ram = databus_ram_VAR;	
            stm_index = stm_index + 1;
         end
      else if (stm_index == 8000) 
         begin
            if (comparator_failure)
               begin
                  $display ("\n Testbench Failed!"); 
               end
            else
               begin
                 $display ("\n Testbench Passed!"); 
               end
	    $finish;
         end
   end

always @(negedge clk)
   begin : comparator

      begin
         {databus_out_VAR, p0_out_VAR, p1_out_VAR, p2_out_VAR, p3_out_VAR, ale_VAR, psen_VAR, rom_addr_VAR, rom_oe_VAR, ram_addr_VAR, ram_we_VAR} = cmp[cmp_index];
         if (databus_out_VAR !== databus_out | p0_out_VAR !== p0_out | 
	     p1_out_VAR !== p1_out | p2_out_VAR !== p2_out | 
	     p3_out_VAR !== p3_out | ale_VAR !== ale | 
	     psen_VAR !== psen | rom_addr_VAR !== rom_addr | 
	     rom_oe_VAR !== rom_oe | ram_addr_VAR !== ram_addr | 
	     ram_we_VAR !== ram_we)
            begin
               comparator_failure = `true;	
            end
     end
     cmp_index = cmp_index + 1;
end

endmodule // module C8051_tb