c8051_td.v

c8051 core 不是源代码版的

module C8051_td (
          rst  ,
          clk  ,
          ea  ,
          p0_in  ,
          p1_in  ,
          p2_in  ,
          p3_in  ,
          databus_rom  ,
          databus_ram  ,
          databus_out  ,
          p0_out  ,
          p1_out  ,
          p2_out  ,
          p3_out  ,
          ale  ,
          psen  ,
          rom_addr  ,
          rom_oe  ,
          ram_addr  ,
          ram_we  ,
          ram_oe 
          );

   input rst ;
   input clk ;
   input ea ;
   input [7:0] p0_in ;
   input [7:0] p1_in ;
   input [7:0] p2_in ;
   input [7:0] p3_in ;
   input [7:0] databus_rom ;
   input [7:0] databus_ram ;
   output [7:0] databus_out ;
   output [7:0] p0_out ;
   output [7:0] p1_out ;
   output [7:0] p2_out ;
   output [7:0] p3_out ;
   output ale ;
   output psen ;
   output [11:0] rom_addr ;
   output rom_oe ;
   output [7:0] ram_addr ;
   output ram_we ;
   output ram_oe ;


   parameter  timingmode = "typ";

   integer tdSig1;

   wire rst ;
   wire clk ;
   wire ea ;
   wire scalared [7:0] p0_in ;
   wire p0_in__7 ,p0_in__6 ,p0_in__5 ,p0_in__4 ,p0_in__3 ,p0_in__2 ,p0_in__1 ,p0_in__0 ;
   assign {p0_in__7 ,p0_in__6 ,p0_in__5 ,p0_in__4 ,p0_in__3 ,p0_in__2 ,p0_in__1 ,p0_in__0 } = p0_in ;
   wire scalared [7:0] p1_in ;
   wire p1_in__7 ,p1_in__6 ,p1_in__5 ,p1_in__4 ,p1_in__3 ,p1_in__2 ,p1_in__1 ,p1_in__0 ;
   assign {p1_in__7 ,p1_in__6 ,p1_in__5 ,p1_in__4 ,p1_in__3 ,p1_in__2 ,p1_in__1 ,p1_in__0 } = p1_in ;
   wire scalared [7:0] p2_in ;
   wire p2_in__7 ,p2_in__6 ,p2_in__5 ,p2_in__4 ,p2_in__3 ,p2_in__2 ,p2_in__1 ,p2_in__0 ;
   assign {p2_in__7 ,p2_in__6 ,p2_in__5 ,p2_in__4 ,p2_in__3 ,p2_in__2 ,p2_in__1 ,p2_in__0 } = p2_in ;
   wire scalared [7:0] p3_in ;
   wire p3_in__7 ,p3_in__6 ,p3_in__5 ,p3_in__4 ,p3_in__3 ,p3_in__2 ,p3_in__1 ,p3_in__0 ;
   assign {p3_in__7 ,p3_in__6 ,p3_in__5 ,p3_in__4 ,p3_in__3 ,p3_in__2 ,p3_in__1 ,p3_in__0 } = p3_in ;
   wire scalared [7:0] databus_rom ;
   wire databus_rom__7 ,databus_rom__6 ,databus_rom__5 ,databus_rom__4 ,databus_rom__3 ,databus_rom__2 ,databus_rom__1 ,databus_rom__0 ;
   assign {databus_rom__7 ,databus_rom__6 ,databus_rom__5 ,databus_rom__4 ,databus_rom__3 ,databus_rom__2 ,databus_rom__1 ,databus_rom__0 } = databus_rom ;
   wire scalared [7:0] databus_ram ;
   wire databus_ram__7 ,databus_ram__6 ,databus_ram__5 ,databus_ram__4 ,databus_ram__3 ,databus_ram__2 ,databus_ram__1 ,databus_ram__0 ;
   assign {databus_ram__7 ,databus_ram__6 ,databus_ram__5 ,databus_ram__4 ,databus_ram__3 ,databus_ram__2 ,databus_ram__1 ,databus_ram__0 } = databus_ram ;
   wire [7:0] databus_out ;
   reg databus_out__7 ,databus_out__6 ,databus_out__5 ,databus_out__4 ,databus_out__3 ,databus_out__2 ,databus_out__1 ,databus_out__0 ;
   assign databus_out = {databus_out__7 ,databus_out__6 ,databus_out__5 ,databus_out__4 ,databus_out__3 ,databus_out__2 ,databus_out__1 ,databus_out__0 };
   wire [7:0] p0_out ;
   reg p0_out__7 ,p0_out__6 ,p0_out__5 ,p0_out__4 ,p0_out__3 ,p0_out__2 ,p0_out__1 ,p0_out__0 ;
   assign p0_out = {p0_out__7 ,p0_out__6 ,p0_out__5 ,p0_out__4 ,p0_out__3 ,p0_out__2 ,p0_out__1 ,p0_out__0 };
   wire [7:0] p1_out ;
   reg p1_out__7 ,p1_out__6 ,p1_out__5 ,p1_out__4 ,p1_out__3 ,p1_out__2 ,p1_out__1 ,p1_out__0 ;
   assign p1_out = {p1_out__7 ,p1_out__6 ,p1_out__5 ,p1_out__4 ,p1_out__3 ,p1_out__2 ,p1_out__1 ,p1_out__0 };
   wire [7:0] p2_out ;
   reg p2_out__7 ,p2_out__6 ,p2_out__5 ,p2_out__4 ,p2_out__3 ,p2_out__2 ,p2_out__1 ,p2_out__0 ;
   assign p2_out = {p2_out__7 ,p2_out__6 ,p2_out__5 ,p2_out__4 ,p2_out__3 ,p2_out__2 ,p2_out__1 ,p2_out__0 };
   wire [7:0] p3_out ;
   reg p3_out__7 ,p3_out__6 ,p3_out__5 ,p3_out__4 ,p3_out__3 ,p3_out__2 ,p3_out__1 ,p3_out__0 ;
   assign p3_out = {p3_out__7 ,p3_out__6 ,p3_out__5 ,p3_out__4 ,p3_out__3 ,p3_out__2 ,p3_out__1 ,p3_out__0 };
   reg ale ;
   reg psen ;
   wire [11:0] rom_addr ;
   reg rom_addr__11 ,rom_addr__10 ,rom_addr__9 ,rom_addr__8 ,rom_addr__7 ,rom_addr__6 ,rom_addr__5 ,rom_addr__4 ,rom_addr__3 ,rom_addr__2 ,rom_addr__1 ,rom_addr__0 ;
   assign rom_addr = {rom_addr__11 ,rom_addr__10 ,rom_addr__9 ,rom_addr__8 ,rom_addr__7 ,rom_addr__6 ,rom_addr__5 ,rom_addr__4 ,rom_addr__3 ,rom_addr__2 ,rom_addr__1 ,rom_addr__0 };
   reg rom_oe ;
   wire [7:0] ram_addr ;
   reg ram_addr__7 ,ram_addr__6 ,ram_addr__5 ,ram_addr__4 ,ram_addr__3 ,ram_addr__2 ,ram_addr__1 ,ram_addr__0 ;
   assign ram_addr = {ram_addr__7 ,ram_addr__6 ,ram_addr__5 ,ram_addr__4 ,ram_addr__3 ,ram_addr__2 ,ram_addr__1 ,ram_addr__0 };
   reg ram_we ;
   reg ram_oe ;



   initial
      $createTDInstance ("./C8051.bin.released");

endmodule