run_nc-verilog

c8051 core 不是源代码版的

rm -rf ./work
mkdir ./work

# Run the NC-Verilog parser (compile the source)
ncvlog -MESSAGES -UPDATE ./C8051_tb.v ./C8051_td.v ./C8051.v

# Run the NC-Verilog elaborator (build the design hierarchy)
ncelab -access +rw -MESSAGES \
       +update C8051_tb \
       -SNAPSHOT worklib.C8051_tb:v 

# Run the NC-Verilog simulator (simulate the design)
ncsim -MESSAGES +update worklib.C8051_tb:v