📄 tb_prog
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//------------------------------------------------------------------
// DSP Address map of UHPI Registers
//------------------------------------------------------------------
#define HPI_LB 0x02A8002C
#define DSP_CFG_BASE 0x0288
#define DSP_PID 0x0000
#define DSP_PWREMU_MGMT 0x0004
#define DSP_HPIC 0x0030
#define DSP_HPIAW 0x0034
#define DSP_HPIAR 0x0038
#define DSP_XHPIAW 0x003C
#define DSP_XHPIAR 0x0040
//------------------------------------------------------------------
// HPI Bif Definitions
// (Required bits' corresponding definitions can be ORed and used)
//------------------------------------------------------------------
#define HPIC_HWOB #0x0001
#define DSP_INT #0x0002
#define HST_INT #0x0004
#define HPIC_HRDY #0x0008
#define HPIC_FETCH #0x0010
#define HPIC_XHPIA #0x0020
#define HPIC_CPURST #0x0040
#define HPIC_HSTRST #0x0080
#define HPIC_HWOBSTS #0x0100
#define HPIC_DUAL #0x0200
#define HPIC_DUAL_RWSEL #0x0A00
#define HPIC_HPIA_RD #0x0800
#define HPIC_HPIA_WR #0x0000
//------------------------------------------------------------------
// Configuration Registers of UHPITB
//------------------------------------------------------------------
#define TB_BASE_ADD #0x030F
#define TB_UHPI_HAIR #0xFFD8
#define TB_UHPI_CSAR #0xFFD4
#define TB_UHPI_CR #0xFFC0
#define TB_UHPI_SR #0xFFD0
#define TB_UHPI_BSAR #0xFFC4
#define TB_UHPI_BLEN #0xFFCC
#define ASYNC_TIME_H #0x0811
#define ASYNC_TIME_L #0x2044
#define GPIO_EN #0xFFE0
//------------------------------------------------------------------
// Bits of TB_UHPI_CR to select the mode
//------------------------------------------------------------------
#define BOOTMODE #0x00000002
#define TBMODE_L #0x0001
#define TBMODE_H #0x0000
#define FASTWRITE_MODE #0x0008
#define FASTREAD_MODE #0x0010
//------------------------------------------------------------------
// Power Down Mode Definations
//-------------------------------------------------------------------
#define PDC_BASE 0x01810000
#define PSC 0x02AE0000
//------------------------------------------------------------------
// Opcodes for loading into SPM command buffer
//------------------------------------------------------------------
#define HPID_WRF_D #0x0000
#define HPID_WRF_P #0x0001
#define HPID_WRB #0x0002
#define HPID_WRB_POLL #0x0003
#define HPID_WRF_POLL_D #0x0004
#define HPID_WRF_POLL_P #0x0005
#define HPIA_WR #0x0006
#define HPIC_WR #0x0007
#define HPID_RDF #0x0008
#define HPID_RDB #0x0009
#define HPID_RDF_POLL #0x000A
#define HPID_RDB_POLL #0x000B
#define HPIA_RD #0x000C
#define HPIC_RD #0x000D
#define HINT_WT #0x000E
#define SLEEP #0x000F
#define TC_END #0xFFFF
//--------------------------------------------------------------
#define XFER_LENGTH #0x0100
#define ZERO #0x0000
#define NUM_BYTES #0x0800
//--------------------------------------------------------------
//............................................................................
#define host_data_h #0x0300
#define host_data_l #0x3000
//#define host_data_dst_h #0x0300
//#define host_data_dst_l #0x2000
#define host_cmd_buff_h #0x0300
#define host_cmd_buff_l #0x1000
#define test_pass_h #0x0300
#define test_pass_l #0x2000
#define dsp_data_src_h #0x0421
#define dsp_data_src_l #0x4000
#define dsp_data_dst_h #0x0421
#define dsp_data_dst_l #0xC000
#define sel_hpia_rd #0x0A00
#define sel_hpia_wr #0x0200
#define dsp_int_dual #0x0202
//**********************************************************************
.main tb_prog
LDI R0.w2, ZERO
LDI R0.w0, ZERO
//
//wait for TBSYNC_IN
WBS #1
//Set TBSYNC_OUT
SET R0, #1
//Wait for TBSYNC_IN to go low
WBC #1
//Clear TBSYNC_OUT
CLR R0, #1
//**********************************************************************
// Load Commands for Burst Write in "host_cmd_buff"
//**********************************************************************
LDI R2.w2, host_cmd_buff_h
LDI R2.w0, host_cmd_buff_l
// Enable DUAL_HPIA and HPIA_RW_SEL -> select HPIA_RD
LDI R1.w2, HPIC_WR
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
ADD R2, R2, #4
LDI R1.w2, sel_hpia_rd
LDI R1.w0, sel_hpia_rd
SBBO R1, R2, #0, 4
ADD R2, R2, #4
// Load HPIA with dsp_dst_add
LDI R1.w2, HPIA_WR
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
ADD R2, R2, #4
LDI R1.w2, dsp_data_src_h
LDI R1.w0, dsp_data_src_l
SBBO R1, R2, #0, 4
ADD R2, R2, #4
// Enable DUAL_HPIA and HPIA_RW_SEL -> select HPIA_WR
LDI R1.w2, HPIC_WR
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
ADD R2, R2, #4
LDI R1.w2, sel_hpia_wr
LDI R1.w0, sel_hpia_wr
SBBO R1, R2, #0, 4
ADD R2, R2, #4
// Load HPIA with dsp_data_add
LDI R1.w2, HPIA_WR
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
ADD R2, R2, #4
LDI R1.w2, dsp_data_dst_h
LDI R1.w0, dsp_data_dst_l
SBBO R1 , R2, #0, 4
ADD R2, R2, #4
// Generating an Interrupt After Initialisation
LDI R1.w2, HPIC_WR
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
ADD R2, R2, #4
LDI R1.w2, ZERO
LDI R1.w0, dsp_int_dual
SBBO R1, R2, #0, 4
ADD R2 , R2 , #4
// Normal Mode Burst Write Access Config Complete
LDI R1.w2, #0xFFFF // TEST BENCH SHUT OFF
LDI R1.w0, #0x0000
SBBO R1 , R2, #0, 4
//**********************************************************************
// Disable GPIO
//**********************************************************************
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, GPIO_EN
LDI R1.w2, ZERO
LDI R1.w0, ZERO
SBBO R1, R2, #0, 4
//**********************************************************************
// Init HPITB Control Registers
//**********************************************************************
// TB_UHPI_CSA register
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_CSAR
LDI R1.w2, host_cmd_buff_h
LDI R1.w0, host_cmd_buff_l
SBBO R1, R2, #0, 4
// TB_UHPI_HAI register
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_HAIR
LDI R1.w2, ASYNC_TIME_H
LDI R1.w0, ASYNC_TIME_L
SBBO R1, R2, #0, 4
// TB_UHPI_BLEN Register
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_BLEN
LDI R1.w2, ZERO
LDI R1.w0, NUM_BYTES
SBBO R1, R2, #0, 4
// TB_UHPI_BSAR Register
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_BSAR
LDI R1.w2, host_data_h
LDI R1.w0, host_data_l
SBBO R1, R2, #0, 4
// 1
//Reset TBSYNC_OUT(GP13), TBSYNC_OUT_GZ(GP13_GZ) and i2c_tester_dut_ready
//wait for TBSYNC_IN
WBS #1
//Set TBSYNC_OUT
SET R0, #1
//Wait for TBSYNC_IN to go low
WBC #1
//Clear TBSYNC_OUT
CLR R0, #1
//TB_UHPI_CR register(NORMAL MODE )
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_CR
LDI R1.w2, TBMODE_H
LDI R1.w0, TBMODE_L
SBBO R1, R2, #0, 4
// wait for test bench to complete transfer
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_SR
label1:
LBBO R1, R2 ,#0 , 4
QBBS label1 ,R1.t1 // QBNE label1 ,R1, #0
//2
// Reset TBSYNC_OUT(GP13), TBSYNC_OUT_GZ(GP13_GZ) and i2c_tester_dut_ready
//wait for TBSYNC_I
WBS #1
//Set TBSYNC_OUT
SET R0, #1
//Wait for TBSYNC_IN to go low
WBC #1
//Clear TBSYNC_OUT
CLR R0, #1
// TB_UHPI_CR register ( FAST MODE READ OPERATION )
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_CR
LDI R1.w2, ZERO
LDI R1.w0, FASTREAD_MODE
SBBO R1, R2, #0, 4
// Wait for test bench to complete Read Operation
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_SR
label2:
LBBO R1, R2 ,#0 , 4
QBBS label2 ,R1.t4 // QBNE label2 ,R1, #0
// 3
//Reset TBSYNC_OUT(GP13), TBSYNC_OUT_GZ(GP13_GZ) and i2c_tester_dut_ready
//wait for TBSYNC_I
WBS #1
//Set TBSYNC_OUT
SET R0, #1
//Wait for TBSYNC_IN to go low
WBC #1
//Clear TBSYNC_OUT
CLR R0, #1
// TB_UHPI_CR register ( FAST MODE WRITE OPERATION )
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_CR
LDI R1.w2, ZERO
LDI R1.w0, FASTWRITE_MODE
SBBO R1, R2, #0, 4
// Wait for test bench to complete Write Operation
LDI R2.w2, TB_BASE_ADD
LDI R2.w0, TB_UHPI_SR
label3:
LBBO R1, R2 ,#0 , 4
QBBS label3 ,R1.t3 // QBNE label3 ,R1, #0
// 4
//Reset TBSYNC_OUT(GP13), TBSYNC_OUT_GZ(GP13_GZ) and i2c_tester_dut_ready
//wait for TBSYNC_I
WBS #1
//Set TBSYNC_OUT
SET R0, #1
//Wait for TBSYNC_IN to go low
WBC #1
//Clear TBSYNC_OUT
CLR R0, #1
STOP:
QBA STOP
.end
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