cache_example.c

dsp tms320c6486的csl例程

                case 7:
                    /* Set L2 cache in normal mode */
                    CACHE_setL2Mode(CACHE_L2_NORMAL);

                    /* read, this data should match data_3 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_3 != Data_4) {
                        printf("CACHE: L2 Normal Mode Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: L2 Normal Mode Passed.\n");
                    }
                    break;

                case 8:
                    /* Writeback invalidate the cache */
                    CACHE_wbInvAllL2(CACHE_WAIT);

                    /* freeze the cache */
                    if(CACHE_setL2Mode(CACHE_L2_FREEZE) != CACHE_L2_NORMAL)
                    {}

                    /* read, this would normally allocate space in the cache */
                    temp = *(Uint32*)EMIF_MEM;
                    *(Uint32*)EMIF_MEM = 0xABCDABCD;

                    /* write to external memory */
                    *(Uint32*)EMIF_MEM =0xA5A5A5A5;
                    if(CACHE_setL2Mode(CACHE_L2_NORMAL) != CACHE_L2_FREEZE)
                    {}
                    Data_4 = *(Uint32*)EMIF_MEM;

                    /* if the cache was frozen then the Data_4 should equal */
                    if(Data_4 != 0xA5A5A5A5) {
                        printf("CACHE: Freeze operation on Cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Freeze operation on Cache Passed.\n");
                    }
                    break;

                default:
                    break;
            }

            /* L2 is turned off */
            CACHE_setL2Size(CACHE_0KCACHE);
            /* disable caching for CE_00 */
            *(Uint32*) 0x01848380 = 0;
        }
    }

    subExampleEndPrint();

    /* Log the result.*/
    if (cacheExampleFail > 0) {
        printf ("\nCACHE: Example on L2 cache FAILED. \
                [Tests Failed: %ld]\n", cacheExampleFail);
    }
    else {
        printf ("\nCACHE: Example on L2 cache PASSED\n");
    }

    exampleEndPrint();

    cacheExampleFail = 0;

    /*========================================================================*
     *                    Test L1D                                            *
     *========================================================================*/

    /* Array used for setting L1 cache size */
    localSize[0] = (CACHE_L2Size)CACHE_L1_4KCACHE;
    localSize[1] = (CACHE_L2Size)CACHE_L1_8KCACHE;
    localSize[2] = (CACHE_L2Size)CACHE_L1_16KCACHE;
    localSize[3] = (CACHE_L2Size)CACHE_L1_32KCACHE;


    /* This loop is used to display the L1 cache size while performing different
     * operations on different L1 cache sizes
     */
    for(loopCount = 0; loopCount <4; loopCount++) {
        switch(loopCount) {
            case 0:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 4K L1 cache.\n");
                subExampleEndPrint();
                break;

            case 1:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 8K L1 cache.\n");
                subExampleEndPrint();
                break;
            case 2:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 16K L1 cache.\n");
                subExampleEndPrint();
                break;

            case 3:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 32K L1 cache.\n");
                subExampleEndPrint();
                break;

            default:
                    break;
        }

        for(count = 1; count <= 6; count++) {
            /* set a test memory location */
            *(Uint32*)EMIF_MEM = 0xABCDABCD;
            Data_2 = 0xa5a5a5a5;

            /* set Mar bit for CACHE_MEM */
            CACHE_enableCaching(CACHE_EMIFA_CE00);

            /* turn on the L1D cache. */
            CACHE_setL1dSize( (CACHE_L1Size)localSize[loopCount]);

            /* read (allocate into cache) */
            Data_1 = *(Uint32*)EMIF_MEM;

            /* write (dirty the cache line) */
            *(Uint32*)EMIF_MEM = Data_2;

            /* Read the data back (make sure it matches Data_2) */
            Data_3 = *(Uint32*)EMIF_MEM;

            if(Data_2 != Data_3)
                printf("CACHE: Data read from cache is not same as \
                        data written.\n");

            switch(count) {
                /* test #1 - invAllL1D */
                case 1:
                    /* Invalidate all L1D cache */
                    CACHE_invAllL1d(CACHE_WAIT);

                    /* read, this data should match data_1 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_1 != Data_4) {
                        printf("CACHE: Invalidate All L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Invalidate All L1D cache Passed.\n");
                    }
                    break;

                /* Test #2 - wbInvAllL1D */
                case 2:
                    /* Writeback invalidate all L1D cache */
                    CACHE_wbInvAllL1d(CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back invalidate All");
                        printf("L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back invalidate All");
                        printf(" L1D cache Passed.\n");
                    }
                    break;

                /* Test #3 wbAll */
                case 3:
                    /* Writeback all L1D cache */
                    CACHE_wbAllL1d(CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back All L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back All L1D cache Passed.\n");
                    }

                    break;

                /* test #4 - invL1D */
                case 4:
                    /* Invalidate L1D cache */
                    CACHE_invL1d((Uint32*)EMIF_MEM,4, CACHE_WAIT);

                    /* read, this data should match data_1 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_1 != Data_4) {
                        printf("CACHE: Invalidate L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Invalidate L1D cache Passed.\n");
                    }
                    break;

                /* Test #5 - wbInv */
                case 5:
                    /* Writeback invalidate L1D cache */
                    CACHE_wbInvL1d((Uint32*)EMIF_MEM,1000, CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back invalidate");
                        printf("L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back invalidate");
                        printf("L1D cache Passed\n");
                    }
                    break;

                /* Test #6 wb */
                case 6:
                    /* Writeback L1D cache */
                    CACHE_wbL1d((Uint32*)EMIF_MEM,1000, CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back L1D cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back L1D cache Passed.\n");
                    }
                    break;

                default:
                    break;
            }

            /* L1D is turned off */
            CACHE_setL1dSize(CACHE_L1_0KCACHE);

            /* disable caching for CE_00 */
            *(Uint32*) 0x01848380 = 0;
        }
    }

    subExampleEndPrint();

    /* Log the result.*/
    if (cacheExampleFail > 0) {
        printf ("\nCACHE: Example on L1 cache FAILED. \
            [Tests Failed: %ld]\n", cacheExampleFail);
    }
    else {
        printf ("\nCACHE: Example on L1 cache PASSED\n");
    }

    exampleEndPrint();
}

void subExampleEndPrint (void)
{
    printf ("*************************************************************\n");
}

void exampleEndPrint (void)
{
    printf ("=============================================================\n");
}