cache_example.c

dsp tms320c6486的csl例程

/*  ===========================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
 *
 *   Use of this software is controlled by the terms and conditions found in
 *   the license agreement under which this software has been supplied.
 *   ==========================================================================
 */

/** ===========================================================================
 *
 *   @file  Cache_example.c
 *
 *   @path  $(CSLPATH)\example\c6486\cache\src
 *
 *   @desc  Example of CACHE
 *
 * ============================================================================
 *   @n <b> Example Description </b>
 *   @n Usage of cache CSL API for the following operations
 *       - Invalidate all L2 and L1D cache
 *       - Write back invalidate all L2 and L1D cache
 *       - Write back all L2 and L1D cache
 *       - Invalidate the L2 and L1D cache
 *       - Write back invalidate L2 and L1D cache
 *       - Write back L2 and L1D cache
 *       - L2 normal mode
 *       - Freeze operation on L2 cache
 *
 * ===========================================================================
 *
 *   <b> Test Procedure </b>
 *   @verbatim
 *      1. Configure the CCS setup to work with the emulator being used
 *      2. Please refer CCS manual for setup configuration and loading
 *         proper GEL file
 *      3. Launch CCS window
 *      4. Open project Cache_example.pjt
 *      5. Build the project and load the .out file of the project.
 *      6. The example can be executed from the main().
 *
 *   @endverbatim
 *
 *
 * =============================================================================
 */

/* ============================================================================
 *  Revision History
 *  ===============
 *  26-Jul-2005 sd     File Created.
 *
 * ============================================================================
 */
#include <stdio.h>
#include <csl_cache.h>
#include <_csl_cache.h>

/* EMIF Memory area */
#define EMIF_MEM        0xE0000000

/* Globals variables used for storing the cache data */
Uint32      temp;
Uint32      Data_1;
Uint32      Data_2;
Uint32      Data_3;
Uint32      Data_4;

/* Foraward declarations */
void subExampleEndPrint(void);
void exampleEndPrint (void);


/*
 * =============================================================================
 *   @func   main
 *
 *   @desc
 *     This is the main routine for the file.
 *
 * =============================================================================
 */

void main(void)
{
    Uint32          cacheExampleFail = 0;
    Uint16          loopCount;
    Uint16          count;
    CACHE_L2Size    localSize[4];


    /* make sure L1P is turned off */
    CACHE_setL1pSize(CACHE_L1_0KCACHE);

    /* make sure that L1D is turned off */
    CACHE_setL1dSize(CACHE_L1_0KCACHE);

    /* make sure that L2 is turned off */
    CACHE_setL2Size(CACHE_0KCACHE);

    /* Array used for setting L2 cache size */
    localSize[0] = CACHE_32KCACHE;
    localSize[1] = CACHE_64KCACHE;
    localSize[2] = CACHE_128KCACHE;
    localSize[3] = CACHE_256KCACHE;

    /* This loop is used to display the L2 cache size while performing different
     * operations on different L2 cache sizes
     */
    for(loopCount = 0; loopCount <4; loopCount++) {
        switch(loopCount) {
            case 0:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 32K L2 cache.\n");
                subExampleEndPrint();
                break;

            case 1:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 64K L2 cache.\n");
                subExampleEndPrint();
                break;
            case 2:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 128K L2 cache.\n");
                subExampleEndPrint();
                break;

            case 3:
                printf("\n");
                subExampleEndPrint();
                printf("CACHE: Performing operations on 256K L2 cache.\n");
                subExampleEndPrint();
                break;

            default:
                break;
        }

        for(count = 1; count <= 7; count++) {
            /* set a test memory location */
            *(Uint32*)EMIF_MEM = 0xABCDABCD;

            Data_2 = 0xa5a5a5a5;

            /* set Mar bit for EMIF_MEM */
            CACHE_enableCaching(CACHE_EMIFA_CE00);

            /* turn on the L2 cache. */
            CACHE_setL2Size( localSize[loopCount]);

            /* read (allocate into cache) */
            Data_1 = *(Uint32*)EMIF_MEM;

            /* write (dirty the cache line) */
            *(Uint32*)EMIF_MEM = Data_2;

            /* Read the data back (make sure it matches Data_2 */
            Data_3 = *(Uint32*)EMIF_MEM;

            if(Data_2 != Data_3)
                printf("CACHE: Data read from cache is not same as \
                        data written.\n");

            switch(count) {
                /* test #1 - invAllL2 */
                case 1:
                    /* Invalidate all the L2 cache */
                    CACHE_invAllL2(CACHE_WAIT);

                    for( temp =0 ; temp < 1000; temp++)
                    {}

                    /* read, this data should match data_1 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_1 != Data_4) {
                        printf("CACHE: Invalidate the All L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Invalidate the All L2 cache Passed.\n");
                    }

                    break;

                /* Test #2 - wbInvAllL2 */
                case 2:
                    /* Writeback invalidate all the L2 cache */
                    CACHE_wbInvAllL2(CACHE_WAIT);

                    for( temp =0 ; temp < 1000; temp++)
                    {}

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back invalidate All");
                        printf("L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back invalidate All");
                        printf("L2 cache Passed.\n");
                    }
                    break;

                /* Test #3 wbAll */
                case 3:
                    /* Writeback all the L2 cache */
                    CACHE_wbAllL2(CACHE_WAIT);

                    for( temp =0 ; temp < 1000; temp++)
                    {}

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4){
                        printf("CACHE: Write back All L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back All L2 cache Passed.\n");
                    }
                    break;

                /* test #4 - invL2 */
                case 4:
                    /* Invalidate the L2 cache */
                    CACHE_invL2((Uint32*)EMIF_MEM, 4, CACHE_WAIT);

                    /* read, this data should match data_1 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_1 != Data_4) {
                        printf("CACHE: Invalidate the L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Invalidate the L2 cache Passed.\n");
                    }
                    break;

                /* Test #5 - wbInv */
                case 5:
                    /* Writeback invalidate the L2 cache */
                    CACHE_wbInvL2((Uint32*)EMIF_MEM,1000, CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back invalidate");
                        printf(" L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back invalidate");
                        printf("L2 cache Passed.\n");
                    }
                    break;

                /* Test #6 wb */
                case 6:
                    /* Writeback L2 cache */
                    CACHE_wbL2((Uint32*)EMIF_MEM, 4, CACHE_WAIT);

                    /* read, this data should match data_2 */
                    Data_4 = *(Uint32*)EMIF_MEM;
                    if(Data_2 != Data_4) {
                        printf("CACHE: Write back L2 cache Failed.\n");
                        cacheExampleFail++;
                    }
                    else {
                        printf("CACHE: Write back L2 cache Passed.\n");
                    }
                    break;

                /* Test #6 wb */