📄 tsip_main.c
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file Tsip_example.c
*
* @path $(CSLPATH)\example\tsip\src
*
* @desc This is an example program for TSIP of CSL 3x.
*
* =============================================================================
*/
#include "test_init.h"
#include <tomahawk.h>
#include <csl_types.h>
#include <csl_psc.h>
//#include "gpio.h"
#include <csl_gpio.h>
#define BufferSize 128
#define GEM_ID 0
CSL_GpioHandle hGpio;
CSL_TsipHandle hTsip0;
CSL_TsipHandle hTsip1;
CSL_TsipHandle hTsip2;
CSL_TsipObj tsipObj0;
CSL_TsipObj tsipObj1;
CSL_TsipObj tsipObj2;
CSL_TsipHwSetup tsipSetup;
CSL_Status status;
CSL_TsipGblSetup gblsetup;
/** Xmt Clock setup */
CSL_TsipXclkSetup xclk;
/** Rcv Clock setup*/
CSL_TsipRclkSetup rclk;
/** Transmit Frame Setup */
CSL_TsipFrameSetup xframesetup;
/** Receive Frame Setup */
CSL_TsipFrameSetup rframesetup;
/** Receive Interrupt Setup */
CSL_TsipIntSetup xint;
/** Receive Interrupt Setup */
CSL_TsipIntSetup rint;
Uint32 ChannelNumber;
//Uint32 xbitmapa0[CSL_TSIP_BITMAP_SIZE];
//Uint32 xbitmapb0[CSL_TSIP_BITMAP_SIZE];
//Uint32 rbitmapa0[CSL_TSIP_BITMAP_SIZE];
//Uint32 rbitmapb0[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapa1[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapb1[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapa1[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapb1[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapa2[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapb2[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapa2[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapb2[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapa3[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapb3[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapa3[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapb3[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapa4[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapb4[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapa4[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapb4[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapa5[CSL_TSIP_BITMAP_SIZE];
Uint32 xbitmapb5[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapa5[CSL_TSIP_BITMAP_SIZE];
Uint32 rbitmapb5[CSL_TSIP_BITMAP_SIZE];
//#pragma DATA_SECTION(Xmt0aSrcAddr, ".data")
//#pragma DATA_ALIGN( Xmt0aSrcAddr, 8)
//Uint32 Xmt0aSrcAddr[736] =
//#include <data_incr.h>
//Uint32 Xmt0aSrcAddr[BufferSize];
Uint32 Rcv0aDestAddr[BufferSize];
Uint32 Xmt0bSrcAddr[BufferSize];
Uint32 Rcv0bDestAddr[BufferSize];
//Uint32 Xmt1aSrcAddr[BufferSize];
Uint32 Rcv1aDestAddr[BufferSize];
Uint32 Xmt1bSrcAddr[BufferSize];
Uint32 Rcv1bDestAddr[BufferSize];
//Uint32 Xmt2aSrcAddr[BufferSize];
Uint32 Rcv2aDestAddr[BufferSize];
Uint32 Xmt2bSrcAddr[BufferSize];
Uint32 Rcv2bDestAddr[BufferSize];
//Uint32 Xmt3aSrcAddr[BufferSize];
Uint32 Rcv3aDestAddr[BufferSize];
Uint32 Xmt3bSrcAddr[BufferSize];
Uint32 Rcv3bDestAddr[BufferSize];
//Uint32 Xmt4aSrcAddr[BufferSize];
Uint32 Rcv4aDestAddr[BufferSize];
Uint32 Xmt4bSrcAddr[BufferSize];
Uint32 Rcv4bDestAddr[BufferSize];
//Uint32 Xmt5aSrcAddr[BufferSize];
Uint32 Rcv5aDestAddr[BufferSize];
Uint32 Xmt5bSrcAddr[BufferSize];
Uint32 Rcv5bDestAddr[BufferSize];
CSL_TsipChanSetup xchannela;
CSL_TsipChanSetup xchannelb;
CSL_TsipChanSetup rchannela;
CSL_TsipChanSetup rchannelb;
Uint32 interruptIteration[6] = {0, 0, 0, 0, 0, 0};
Uint32 arg;
Uint32 channel;
volatile Uint32 TsipDone = 0;
Uint32 result = 0;
Uint32 TSIP_ID = 0;
Uint32 bitmappos = 0;
Uint32* SrcDataIncPtr;
void tsip_basic_setup();
void tsip_Channel_setup();
void CID_Init();
Uint32 DoTest(void);
void set_design_done ();
Uint32 DoTest()
{
// Uint32 i,j;
Uint32 TraceCounter = 0;
if (GEM_ID == 0)
{
// TB Synchronisation-> Setting GPIO 12 as O/p and 13 as I/P
// CSL_GPIO_REGS->DIR = 0x2000; //@NG
set_design_done(
);
/* Initialise Source Buffer */
Init_Mem((Xmt0aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize, 0x1);
// Init_Mem((Xmt0aSrcAddr) ,1, BufferSize, 0x1);
Init_Mem((Xmt1aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize, 0x1);
Init_Mem((Xmt2aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize, 0x1);
Init_Mem((Xmt3aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize, 0x1);
Init_Mem((Xmt4aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize, 0x1);
Init_Mem((Xmt5aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4) ,1, BufferSize * 2 , 0x1);
/* Enable LPSC domains of 3 TSIPs */
TSIP_Domain_Enable();
hTsip0 = CSL_tsipOpen(&tsipObj0, CSL_TSIP_0, NULL, &status);
tsip_basic_setup();
hTsip1 = CSL_tsipOpen(&tsipObj1, CSL_TSIP_1, NULL, &status);
hTsip2 = CSL_tsipOpen(&tsipObj2, CSL_TSIP_2, NULL, &status);
CSL_tsipHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[0].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[1].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[2].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[3].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[4].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
tsip_Channel_setup(Test_List[5].ChannelNumber);
CSL_tsipChHwSetup(hTsip0, &tsipSetup);
CID_Init();
// Enabling IOLB Mode */
//arg = 0x0;
//CSL_FINS(hTsip0->regs->EMUTST, TSIP_EMUTST_IOLB, arg);
//arg = 0x1;
//CSL_FINS(hTsip0->regs->EMUTST, TSIP_EMUTST_SIUTST, arg);
arg = 0x1;
CSL_FINS( hTsip0->regs->SIUCTL, TSIP_SIUCTL_XMTENB, arg );
CSL_FINS( hTsip0->regs->SIUCTL, TSIP_SIUCTL_RCVENB, arg );
setup_Tsip_Interrupt();
arg = 1;
CSL_tsipHwControl(hTsip0, CSL_TSIP_CMD_ENA_DMA, &arg);
// TB Synchronisation-> Setting GPIO 12
// CSL_GPIO_REGS->OUT_DATA = 0x1000; //@NG
// TB Synchronisation-> Setting GPIO 12
// CSL_GPIO_REGS->OUT_DATA = 0x0000; //@NG
set_design_done(
);
while(TsipDone == 0) {
TraceCounter++;
//if (TraceCounter == 0x1500)
//CSL_FINSR((*((Uint32 *)0x02b00014)), 15, 15, 1);
}
result = Verify_Transfer((Test_List[0].xmt_frame_count ), ((Test_List[0].xmt_frame_size + 9)), (Xmt0aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv0aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
//CSL_FINSR((*((Uint32 *)0x02b00014)), 15, 15, 1);
result += Verify_Transfer((Test_List[1].xmt_frame_count ), ((Test_List[1].xmt_frame_size + 9)), (Xmt1aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv1aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
result += Verify_Transfer((Test_List[2].xmt_frame_count ), ((Test_List[2].xmt_frame_size + 9)), (Xmt2aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv2aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
result += Verify_Transfer((Test_List[3].xmt_frame_count ), ((Test_List[3].xmt_frame_size + 9)), (Xmt3aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv3aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
result += Verify_Transfer((Test_List[4].xmt_frame_count ), ((Test_List[4].xmt_frame_size + 9)), (Xmt4aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv4aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
result += Verify_Transfer((Test_List[5].xmt_frame_count ), ((Test_List[5].xmt_frame_size + 9)), (Xmt5aSrcAddr + GEM_ID * 0x1000000/4 + 0x10000000/4), (Rcv5aDestAddr + GEM_ID * 0x1000000/4 + 0x10000000/4));
}
return (result);
}
void tsip_basic_setup()
{
// Uint32* datainput0ptr;
// Uint32* datainput1ptr;
// Uint32* Expdata0ptr;
// Uint32* Expdata1ptr;
// Uint32 i, j;
tsipSetup.gbl = &gblsetup;
tsipSetup.xframe = &xframesetup;
tsipSetup.rframe = &rframesetup;
tsipSetup.xclk = &xclk;
tsipSetup.rclk = &rclk;
tsipSetup.xint = &xint;
tsipSetup.rint = &rint;
xframesetup.fcount = (CSL_TsipFramecount)3;
xframesetup.fsize = (CSL_TsipFramesize)127;
rframesetup.fcount = (CSL_TsipFramecount)3;
rframesetup.fsize = (CSL_TsipFramesize)127;
gblsetup.clkd = (CSL_TsipClkd)Tsip0.ClockDiv;
gblsetup.endian = (CSL_TsipEndian)Tsip0.Endian;
gblsetup.pri = (CSL_TsipPri)Tsip0.priority;
gblsetup.maxpri = (CSL_TsipPri)Tsip0.max_priority;
xclk.clksrc = (CSL_TsipClkSrc)Tsip0.xclk_clksrc;
xclk.datd = Tsip0.xclk_datadelay;
xclk.outdis = (CSL_TsipXmtDis)Tsip0.xclk_outdis;
xclk.fsyncp = (CSL_TsipFsyncp)Tsip0.xclk_fsyncp;
xclk.fclkp = (CSL_TsipClkp)Tsip0.xclk_fclkp;
xclk.dclkp = (CSL_TsipClkp)Tsip0.xclk_dclkp;
xclk.drate = (CSL_TsipDataRate)Tsip0.xclk_drate;
xclk.clkmode = (CSL_TsipClkm)Tsip0.xclk_clkmode;
rclk.clksrc = (CSL_TsipClkSrc)Tsip0.rclk_clksrc;
rclk.datd = Tsip0.rclk_datadelay;
rclk.fsyncp = (CSL_TsipFsyncp)Tsip0.rclk_fsyncp;
rclk.fclkp = (CSL_TsipClkp)Tsip0.rclk_fclkp;
rclk.dclkp = (CSL_TsipClkp)Tsip0.rclk_dclkp;
rclk.drate = (CSL_TsipDataRate)Tsip0.rclk_drate;
rclk.clkmode = (CSL_TsipClkm)Tsip0.rclk_clkmode;
xint.sfint = (CSL_TsipInt)0;
xint.frint = (CSL_TsipInt)0;
xint.fdelay = (CSL_TsipInt)0;
rint.sfint = (CSL_TsipInt)0;
rint.frint = (CSL_TsipInt)0;
rint.fdelay = (CSL_TsipInt)0;
}
void tsip_Channel_setup(Uint32 ChannelNumber)
{
Uint32 randomnumber;
Uint32 bitmap;
Uint32 bitmapcount;
// Uint32 InputDataInc;
Uint32 FrameSize;
// Uint32 FrameCount;
// Uint8 DataInc;
Uint32 j;
channel = ChannelNumber;
tsipSetup.ChannelNumber = &channel;
switch(channel) {
case 0 :
{
xchannela.baseaddr = (Uint32) (Xmt0aSrcAddr + GEM_ID * 0x1000000 + 0x10000000);
rchannela.baseaddr = (Uint32) (Rcv0aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt0aSrcAddr;
break;
}
case 1 :
{
xchannela.baseaddr = (Uint32) (Xmt1aSrcAddr + GEM_ID * 0x1000000 + 0x10000000) ;
rchannela.baseaddr = (Uint32) (Rcv1aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt1aSrcAddr;
break;
}
case 2 :
{
xchannela.baseaddr = (Uint32) (Xmt2aSrcAddr + GEM_ID * 0x1000000 + 0x10000000);
rchannela.baseaddr = (Uint32) (Rcv2aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt2aSrcAddr;
break;
}
case 3 :
{
xchannela.baseaddr = (Uint32) (Xmt3aSrcAddr + GEM_ID * 0x1000000 + 0x10000000);
rchannela.baseaddr = (Uint32) (Rcv3aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt3aSrcAddr;
break;
}
case 4 :
{
xchannela.baseaddr = (Uint32) (Xmt4aSrcAddr + GEM_ID * 0x1000000 + 0x10000000);
rchannela.baseaddr = (Uint32) (Rcv4aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt4aSrcAddr;
break;
}
case 5 :
{
xchannela.baseaddr = (Uint32) (Xmt5aSrcAddr + GEM_ID * 0x1000000 + 0x10000000);
rchannela.baseaddr = (Uint32) (Rcv5aDestAddr + GEM_ID * 0x1000000 + 0x10000000);
SrcDataIncPtr = Xmt5aSrcAddr;
break;
}
default :
break;
}
// CID + FC at the header and footer
xchannela.falloc = (Test_List[channel].xmt_frame_size + 9) ;
xchannela.fsize = (Test_List[channel].xmt_frame_size + 9) ;
rchannela.falloc = (Test_List[channel].xmt_frame_size + 9) ;
rchannela.fsize = (Test_List[channel].xmt_frame_size + 9) ;
//considering first dummy frame
xchannela.fcount = Test_List[channel].xmt_frame_count + 2;
rchannela.fcount = Test_List[channel].xmt_frame_count + 2;
/* Generate random bitmaps for the corresponding frame size */
bitmapcount = 0;
FrameSize = Test_List[channel].xmt_frame_size + 1;
bitmap = 0;
for (j = 0; ((j < CSL_TSIP_BITMAP_SIZE * 16)); j++) {
if ((bitmapcount < FrameSize) && (j >= bitmappos)) {
//randomnumber = rand()%2;
randomnumber = 0x01;
if ((randomnumber != 0)) {
bitmapcount++;
}
bitmap |= (randomnumber << ((j%16)*2));
}
if ((j % 16) == 15) {
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