test_init.h

dsp tms320c6486的csl例程

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */
#include "csl_tsip.h"
#include "csl_tsipAux.h"

#include "cslr_gpio.h"
#include "cslr_tsip.h"
#include "tomahawk.h"
  
#define BUFF_SIZE (1024)
#define NUM_CELL     (4)

#pragma DATA_SECTION(Xmt0aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt0aSrcAddr, 8)
Uint32               Xmt0aSrcAddr[1024] =
#include <data_incr.h>

#pragma DATA_SECTION(Xmt1aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt1aSrcAddr, 8)
Uint32               Xmt1aSrcAddr[1024] =
#include <data_incr.h>

#pragma DATA_SECTION(Xmt2aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt2aSrcAddr, 8)
Uint32               Xmt2aSrcAddr[1024] =
#include <data_incr.h>

#pragma DATA_SECTION(Xmt3aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt3aSrcAddr, 8)
Uint32               Xmt3aSrcAddr[1024] =
#include <data_incr.h>

#pragma DATA_SECTION(Xmt4aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt4aSrcAddr, 8)
Uint32               Xmt4aSrcAddr[1024] =
#include <data_incr.h>

#pragma DATA_SECTION(Xmt5aSrcAddr, "data")
#pragma DATA_ALIGN(  Xmt5aSrcAddr, 8)
Uint32               Xmt5aSrcAddr[1024] =
#include <data_incr.h>


#pragma DATA_SECTION(xbitmapa0, "data")
#pragma DATA_ALIGN(  xbitmapa0, 8)
Uint32               xbitmapa0[64] =
#include <data_bitmap.h>

#pragma DATA_SECTION(xbitmapb0, "data")
#pragma DATA_ALIGN(  xbitmapb0, 8)
Uint32               xbitmapb0[64] =
#include <data_bitmap.h>

#pragma DATA_SECTION(rbitmapa0, "data")
#pragma DATA_ALIGN(  rbitmapa0, 8)
Uint32               rbitmapa0[64] =
#include <data_bitmap.h>

#pragma DATA_SECTION(rbitmapb0, "data")
#pragma DATA_ALIGN(  rbitmapb0, 8)
Uint32               rbitmapb0[64] =
#include <data_bitmap.h>

#define TIMESLOTS_IN_LINK0 31
#define TIMESLOTS_IN_LINK1 39
#define TIMESLOTS_IN_LINK2 27
#define TIMESLOTS_IN_LINK3 35
#define TIMESLOTS_IN_LINK4 43
#define TIMESLOTS_IN_LINK5 31

//#define Xmt0_Frame_Count 3
//#define Xmt1_Frame_Count 2
//#define Xmt2_Frame_Count 4
//#define Xmt3_Frame_Count 1
//#define Xmt4_Frame_Count 5
//#define Xmt5_Frame_Count 6

//#define TIMESLOTS_IN_LINK0 15
//#define TIMESLOTS_IN_LINK1 15
//#define TIMESLOTS_IN_LINK2 15
//#define TIMESLOTS_IN_LINK3 15
//#define TIMESLOTS_IN_LINK4 15
//#define TIMESLOTS_IN_LINK5 15

#define Xmt0_Frame_Count 3
#define Xmt1_Frame_Count 3
#define Xmt2_Frame_Count 3
#define Xmt3_Frame_Count 3
#define Xmt4_Frame_Count 3
#define Xmt5_Frame_Count 3

#define MAX_FRAME_COUNT 3

#define Xmt0_Frame_Size  TIMESLOTS_IN_LINK0

#define Xmt1_Frame_Size  TIMESLOTS_IN_LINK1

#define Xmt2_Frame_Size  TIMESLOTS_IN_LINK2

#define Xmt3_Frame_Size  TIMESLOTS_IN_LINK3

#define Xmt4_Frame_Size  TIMESLOTS_IN_LINK4

#define Xmt5_Frame_Size  TIMESLOTS_IN_LINK5

typedef struct { 
   Uint32 ClockDiv; 
   Uint32 Endian;
   Uint32 priority;	
   Uint32 max_priority;
   Uint32 xclk_clksrc;
   Uint32 xclk_datadelay;
   Uint32 xclk_outdis;
   Uint32 xclk_fsyncp;
   Uint32 xclk_fclkp;
   Uint32 xclk_dclkp;
   Uint32 xclk_drate;
   Uint32 xclk_clkmode;
   Uint32 rclk_clksrc;
   Uint32 rclk_datadelay;
   Uint32 rclk_fsyncp;
   Uint32 rclk_fclkp;
   Uint32 rclk_dclkp;
   Uint32 rclk_drate;
   Uint32 rclk_clkmode;
      
} tsip_setup; 

typedef struct { 
   Uint32 ChannelNumber; 
   Uint32 xmt_frame_count;	
   Uint32 xmt_frame_size;
   Uint32 rcv_frame_count;	
   Uint32 rcv_frame_size;
} tsip_channel_setup; 

tsip_setup Tsip0 = {
                               CSL_TSIP_CLKD_REDUN,
                               CSL_TSIP_ENDIAN_LITTLE,
                               CSL_TSIP_PRI_1,
                               CSL_TSIP_PRI_1,
                               CSL_TSIP_CLKSRC_A,
                               0x0,
                               CSL_TSIP_XCTL_DIS_HIMPED,
                               CSL_TSIP_XCTL_FSYNCP_ALOW,
                               CSL_TSIP_XCTL_FCLKP_RISING,
                               CSL_TSIP_RCTL_DCLKP_RISING,
                               CSL_TSIP_DATARATE_16M,
                               CSL_TSIP_XCTL_CLKM_SGL,
                               CSL_TSIP_CLKSRC_A,
                               0x0,
                               CSL_TSIP_XCTL_FSYNCP_ALOW,
                               CSL_TSIP_XCTL_FCLKP_RISING,
                               CSL_TSIP_RCTL_DCLKP_RISING,
                               CSL_TSIP_DATARATE_16M,
                               CSL_TSIP_XCTL_CLKM_SGL,
                               };
 
tsip_channel_setup  Test_List[6] = {
                               // Link 0
                               { 
                               0x0,
                               Xmt0_Frame_Count, 
                               Xmt0_Frame_Size, 
                               Xmt0_Frame_Count, 
                               Xmt0_Frame_Size , 
                               },
                               // Link 1
                               { 
                               0x1,
                               Xmt1_Frame_Count, 
                               Xmt1_Frame_Size, 
                               Xmt1_Frame_Count, 
                               Xmt1_Frame_Size , 
                               },
                               // Link 2
                               { 
                               0x2,
                               Xmt2_Frame_Count, 
                               Xmt2_Frame_Size, 
                               Xmt2_Frame_Count, 
                               Xmt2_Frame_Size , 
                               },

                               // Link 3
                               { 
                               0x3,
                               Xmt3_Frame_Count, 
                               Xmt3_Frame_Size, 
                               Xmt3_Frame_Count, 
                               Xmt3_Frame_Size , 
                               },

                               // Link 4
                               { 
                               0x4,
                               Xmt4_Frame_Count, 
                               Xmt4_Frame_Size, 
                               Xmt4_Frame_Count, 
                               Xmt4_Frame_Size , 
                               },

                               // Link 5
                               { 
                               0x5,
                               Xmt5_Frame_Count, 
                               Xmt5_Frame_Size, 
                               Xmt5_Frame_Count, 
                               Xmt5_Frame_Size , 
                               }
                               };
	 
#define NUM_LINKS     sizeof(Test_List)/sizeof(tsip_channel_setup)  

/*****************************************************************************\
* End of test_init.h
\*****************************************************************************/