📄 ezkitbf5xx_initcode.asm
字号:
Return: R0 = RDIV_VAL
*****************************************************************************/
_GET_RDIV:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:1,P5:5);
call _GET_SCLK_Hz; /* R0 = current SCLK [Hz] */
R1 = NRA (z);
R7 = 1000 (z);
R1 *= R7;
udiv32();
R7 = tREF (z); /* R7 = tREF [ms] */
R0 *= R7; /* R0 = ( SCLK / NRA ) * tREF */
IMM32(R7,EBIU_SDGCTL_VAL);
/* get tRP */
R5 = 0x00003800;
R5 = R5 & R7;
R5 >>= 11; /* R5 = tRP */
/* get tRAS */
R6 = 0x000003C0;
R6 = R6 & R7;
R6 >>= 6; /* R6 = tRAS */
R7 = R5 + R6; /* R7 = tRAS + tRP */
R0 = R0 - R7; /* R0 = RDIV */
(R7:1,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_GET_RDIV.end:
/*****************************************************************************
PLL
*****************************************************************************/
/*****************************************************************************
Prototypes
******************************************************************************/
//.GLOBAL _GET_VCO_Hz;
//.GLOBAL _GET_CCLK_Hz;
//.GLOBAL _GET_SCLK_Hz;
/*****************************************************************************
Functions
******************************************************************************/
.section L1_code;
/****************************************************************************
Name: _GET_VCO_Hz
Description: get PLL VCO frequency in Hz
Return: R0 = VCO
*****************************************************************************/
_GET_VCO_Hz:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:6,P5:5);
/* get current MSEL */
P5.H = hi(PLL_CTL);
P5.L = lo(PLL_CTL);
R7 = w[P5] (z);
R0 = 0x7E00 (z);
R0 = R0 & R7;
R0 >>= 9; /* R0 = current MSEL */
/* get current VCO */
IMM32(R6,CLKIN_Hz); /* R6 = CLKIN [Hz] */
R0 *= R6; /* R0 = MSEL * CLKIN */
R6 = 0x1 (z); /* R6 = DF bit */
R6 = R6 & R7; /* R6 = DF bit [1/0] */
R0 >>= R6; /* R0 = current VCO [Hz] */
(R7:6,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_GET_VCO_Hz.end:
/****************************************************************************
Name: _GET_CCLK_Hz
Description: get core clock frequency in Hz
Return: R0 = CCLK
*****************************************************************************/
_GET_CCLK_Hz:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:6,P5:5);
P5.H = hi(PLL_CTL);
P5.L = lo(PLL_CTL);
R7 = w[P5] (z);
CC = bittst(R7,bitpos(BYPASS));
IMM32(R0,CLKIN_Hz);
if CC jump _GET_CCLK_Hz.skip;
call _GET_VCO_Hz; /* R0 = current VCO [Hz] */
/* get current CSEL */
R7 = w[P5 + PLL_DIV - PLL_CTL] (z);
R6 = 0x0030 (z);
R7 = R7 & R6;
R7 >>= 4; /* R7 = current CSEL */
R0 >>= R7; /* R0 = current CCLK */
_GET_CCLK_Hz.skip:
(R7:6,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_GET_CCLK_Hz.end:
/****************************************************************************
Name: _GET_SCLK_Hz
Description: get system clock frequency in Hz
Return: R0 = SCLK
*****************************************************************************/
_GET_SCLK_Hz:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:1,P5:5);
P5.H = hi(PLL_CTL);
P5.L = lo(PLL_CTL);
R7 = w[P5] (z);
CC = bittst(R7,bitpos(BYPASS));
IMM32(R0,CLKIN_Hz);
if CC jump _GET_SCLK_Hz.skip;
call _GET_VCO_Hz; /* R0 = current VCO [Hz] */
/* get current SSEL */
R1 = w[P5 + PLL_DIV - PLL_CTL] (z);
R7 = 0x000F(z);
R1 = R1 & R7; /* R1 = current SSEL */
/* get current SCLK */
udiv32(); /* Registers passed: Dividend = R0, Divisor = R1, Quotient -> R0 */
/* R0 = current SCLK */
_GET_SCLK_Hz.skip:
(R7:1,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_GET_SCLK_Hz.end:
/*****************************************************************************
Mode 'Boot from UART host (slave mode)'
ADSP-BF527 & ADSP-BF537 EZ-KIT Lite only
*****************************************************************************/
#if defined (__ADSPBF527__) || defined (__ADSPBF537__)
/*****************************************************************************
Global Variables
******************************************************************************/
//.GLOBAL _b4_UART_BIT_RATE;
/*****************************************************************************
Variables
******************************************************************************/
.SECTION L1_data;
.ALIGN 4;
.BYTE4 _b4_UART_BIT_RATE;
/*****************************************************************************
Prototypes
******************************************************************************/
//.GLOBAL _GET_UART_BITRATE;
//.GLOBAL _SET_UART_BITRATE;
/*****************************************************************************
Functions
******************************************************************************/
.section L1_code;
/****************************************************************************
Name: _GET_UART_BITRATE
Description: get UART Bit Rate
Return: R0 = UART Divisor * 16 = BIT RATE
Stored Value: _b4_UART_BIT_RATE = R0 = UART Divisor * 16 = BIT RATE
*****************************************************************************/
_GET_UART_BITRATE:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:0,P5:5);
#if defined __ADSPBF527__
_GET_UART_BITRATE.UART1_Boot:
P5.H = hi(SYSCR);
P5.L = lo(SYSCR);
R7 = w[P5] (z);
R6 = 0xF (z); /* BMODE [3:0] */
R7 = R6 & R7;
R6 = 0x8 (z); /* ADSP-BF527: BMODE [3:0] = 1000 - Boot from UART1 host (slave mode) */
R6 = R6 & R7;
CC = R6 == R7;
if !CC jump _GET_UART_BITRATE.UART0_Boot;
/* Set Divisor Latch Access Bit in UART1_LCR */
P5.H = hi(UART1_LCR);
P5.L = lo(UART1_LCR);
R5 = w[P5] (z);
bitset(R5,bitpos(DLAB));
w[P5] = R5;
R7 = w[P5 + UART1_DLH - UART1_LCR] (z);
R6 = w[P5 + UART1_DLL - UART1_LCR] (z);
/* Combine UART Divisor to UART1_DLH & UART1_DLL */
R7 <<= 8;
R1 = R7 | R6;
R7 = 0x10 (z);
R1 *= R7;
/* Clear Divisor Latch Access Bit in UART1_LCR */
bitclr(R5,bitpos(DLAB));
w[P5] = R5;
jump _GET_UART_BITRATE.UART0_Boot.skip;
#endif
_GET_UART_BITRATE.UART0_Boot:
/* Set Divisor Latch Access Bit in UART0_LCR */
P5.H = hi(UART0_LCR);
P5.L = lo(UART0_LCR);
R5 = w[P5] (z);
bitset(R5,bitpos(DLAB));
w[P5] = R5;
R7 = w[P5 + UART0_DLH - UART0_LCR] (z);
R7 <<= 8;
R6 = w[P5 + UART0_DLL - UART0_LCR] (z);
/* Combine UART Divisor to UART0_DLH & UART0_DLL */
R1 = R7 | R6;
R7 = 0x10 (z);
R1 *= R7;
/* Clear Divisor Latch Access Bit in UART0_LCR */
bitclr(R5,bitpos(DLAB));
w[P5] = R5;
_GET_UART_BITRATE.UART0_Boot.skip:
call _GET_SCLK_Hz; /* R0 = current SCLK [Hz] */
/* get current UART Bit Rate */
udiv32(); /* Registers passed: Dividend = R0, Divisor = R1, Quotient -> R0 */
/* Save UART Bit Rate */
P5.H = hi(_b4_UART_BIT_RATE);
P5.L = lo(_b4_UART_BIT_RATE);
[P5] = R0;
(R7:0,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_GET_UART_BITRATE.end:
/****************************************************************************
Name: _SET_UART_BITRATE
Description: calculate and set UART Divisor latch registers
UART0_DLH & UART0_DLL that fits former Bit Rate
and new system clock
*****************************************************************************/
_SET_UART_BITRATE:
link 0;
[--SP] = ASTAT;
[--SP] = (R7:0,P5:5);
call _GET_SCLK_Hz; /* R0 = current SCLK [Hz] */
P5.H = hi(_b4_UART_BIT_RATE);
P5.L = lo(_b4_UART_BIT_RATE);
R1 = [P5];
/* calculate new UART Divisor */
/* Divide SCLK [Hz] by 16 * Bit Rate */
R7 = 0x10;
R1 *= R7;
udiv32(); /* Registers passed: Dividend = R0, Divisor = R1, Quotient -> R0 */
#if defined __ADSPBF527__
_SET_UART_BITRATE.UART1_Boot:
P5.H = hi(SYSCR);
P5.L = lo(SYSCR);
R7 = w[P5] (z);
R6 = 0xF (z); /* BMODE [3:0] */
R7 = R6 & R7;
R6 = 0x8 (z); /* ADSP-BF527: BMODE [3:0] = 1000 - Boot from UART1 host (slave mode) */
R6 = R6 & R7;
CC = R6 == R7;
if !CC jump _SET_UART_BITRATE.UART0_Boot;
/* Set Divisor Latch Access Bit in UART1_LCR */
P5.H = hi(UART1_LCR);
P5.L = lo(UART1_LCR);
R5 = w[P5] (z);
bitset(R5,bitpos(DLAB));
w[P5] = R5;
/* Split UART Divisor to UART1_DLH & UART1_DLL */
R7 = 0xFF00 (z);
R7 = R0 & R7;
R7 >>= 8;
w[P5 + UART1_DLH - UART1_LCR] = R7;
R7 = 0xFF (z);
R7 = R0 & R7;
w[P5 + UART1_DLL - UART1_LCR] = R7;
/* Clear Divisor Latch Access Bit in UART1_LCR */
bitclr(R5,bitpos(DLAB));
w[P5] = R5;
jump _SET_UART_BITRATE.UART0_Boot.skip;
#endif
_SET_UART_BITRATE.UART0_Boot:
/* Set Divisor Latch Access Bit in UART0_LCR */
P5.H = hi(UART0_LCR);
P5.L = lo(UART0_LCR);
R5 = w[P5] (z);
bitset(R5,bitpos(DLAB));
w[P5] = R5;
/* Split UART Divisor to UART0_DLH & UART0_DLL */
R7 = 0xFF00 (z);
R7 = R0 & R7;
R7 >>= 8;
w[P5 + UART0_DLH - UART0_LCR] = R7;
R7 = 0xFF (z);
R7 = R0 & R7;
w[P5 + UART0_DLL - UART0_LCR] = R7;
/* Clear Divisor Latch Access Bit in UART0_LCR */
bitclr(R5,bitpos(DLAB));
w[P5] = R5;
_SET_UART_BITRATE.UART0_Boot.skip:
(R7:0,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;
_SET_UART_BITRATE.end:
#endif /* defined (__ADSPBF527__) || defined (__ADSPBF537__) */
/****************************************************************************
EOF
*****************************************************************************/
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