ezkitbf5xx_initcode.asm

关于bf531的好程序

/*****************************************************************************
**                                                                          **
**  Name:   ezkitBF5xx_initcode EXAMPLE                                     **
**                                                                          **
******************************************************************************

(C) Copyright 2007 - Analog Devices, Inc.  All rights reserved.

Project Name:   ezkitBF5xx_initcode

Version:        v1.0beta

Last Modified:  11/29/07 ap-muc

History:        05/22/07 v0.0 ap-muc

Tested
Software:       VisualDSP++ 4.5.5.0 (Updated June 2007)
                VisualDSP++ 5.0.0.0
                VisualDSP++ 5.0.1.0 (Update 1)

Tested
Hardware:       ADSP-BF527 EZ-KIT Lite Rev. 1.0 Silicon Rev. 0.0
                ADSP-BF533 EZ-KIT Lite Rev. 1.7 Silicon Rev. 0.4
                ADSP-BF533 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5
                ADSP-BF537 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.2
                ADSP-BF538 EZ-KIT Lite Rev. 1.2 Silicon Rev. 0.3
                ADSP-BF561 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.3
                ADSP-BF561 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5

Supported
Plattforms:     ADSP-BF527 EZ-KIT Lite
                ADSP-BF533 EZ-KIT Lite Rev 1.7 and above
                ADSP-BF533 EZ-KIT Lite Rev 1.6 and below (modifications required, only 32MB SDRAM installed)
                ADSP-BF537 EZ-KIT Lite
                ADSP-BF538 EZ-KIT Lite
                ADSP-BF561 EZ-KIT Lite (Silicon Rev. 0.2 and beyond)

Connections:    ADDS-HPUSB-ICE

Software
Settings:       default

Project
Properties:     Assemble -> Additional include directories -> $(VDSP)\Blackfin\lib\src\libdsp\

Hardware
Settings:       default

Purpose /
Description:    General Initialization example for ADSP-BF5xx EZ-KIT Lite (excluding ADSP-BF54x EZ-KIT Lite)
                Included are:
                - PLL Settings (optimized for high speed)
                - Voltage Regulator Settings
                - EBIU settings for the EZ-KIT Lite (Asynchronous and SDRAM memory)
                - Bit Rate handler for Mode 'Boot from UART host (slave mode)' (ADSP-BF527 & ADSP-BF537 EZ-KIT Lite only)

Hint for
ADSP-BF561:     Init code is supported beginning with the November update of VisualDSP++
                Please read EE-314: Booting the ADSP-BF561 Blackfin Processor.
                Required Loader Switches (Project Options->Load->Options->Addtidional Options): -NoFinalTag, -nosecondstagekernel
                For changing PLL settings it is absolutly necessary, that Core B is in idle mode !!!
                The programmer has to take care of this !!!
                This init code assumes that Core B is in idle state (as it is immediately after booting) !!!

Restrictions:   - For ADSP-BF561 EZ-KIT Lite & ADSP-BF527 EZ-KIT Lite: Wait states for async flash interface are not optimized yet. Default/Save settings are still included

*****************************************************************************/


/*****************************************************************************
 Include Files
******************************************************************************/

/* see specific header files in the project folders */

/*****************************************************************************
 Symbolic constants & definitions
******************************************************************************/

/*****************************************************************************
 macros
******************************************************************************/

/* Load Immediate 32-bit value into data or address register */
#define IMM32(reg,val) reg##.H=hi(val); reg##.L=lo(val)

/* ___udiv32 manipulates some data registers and pointer registers without saving theme as the C-Runtime environment is taking care of this */
#define udiv32() [--SP] = (R7:1,P5:0); call ___udiv32; (R7:1,P5:0) = [SP++]


/*****************************************************************************
 External Functions
******************************************************************************/

#include "udiv32.asm" /* C-Library function in \Blackfin\lib\src\libdsp\udiv32.asm, R0 = Dividend, R1 = Divisor, Quotient -> R0 */


/****************************************************************************
 Main Program
*****************************************************************************/

.GLOBAL _initcode;


.section L1_code;


_initcode:


/*****************************************************************************
 Pre-Init Section
 Save all used register on the stack
******************************************************************************/

link 0;
[--SP] = ASTAT;
[--SP] = (R7:0,P5:5);


/************************************************
* System Interrupt Wakeup Registers (SIC_IWRx)  *
* Required for PLL_CTL and VR_CTL configuration *
* Processor idle and wake up after PLL_LOCKCNT  *
* expired.Reset = 0xFFFF FFFF                   *
* disable all other interrupt sources in the    *
* meantime to disable unwanted wake up events   *
************************************************/

P5.H = hi(SIC_IWR0);
P5.L = lo(SIC_IWR0);

R7 = 0x0;

#if defined (__ADSPBF527__) || defined (__ADSPBF561__)
    [P5 + SIC_IWR1 - SIC_IWR0] = R7;
#endif

bitset(R7,bitpos(PLL_WAKEUP_IRQ));
[P5] = R7; /* enable PLL Wakeup Interrupt */


/*************************************************
 Test for Boot Modes that reuqire special actions
*************************************************/

#if defined (__ADSPBF527__) || defined (__ADSPBF537__)

    P5.H = hi(SYSCR);
    P5.L = lo(SYSCR);

    R7 = w[P5] (z);
    #if defined __ADSPBF527__
        R6 = 0xF (z); /* BMODE [3:0] */
    #elif defined __ADSPBF537__
        R6 = 0x7 (z); /* BMODE [2:0] */
    #endif
    R7 = R6 & R7;

    /*************************************************
     UART Host Boot mode: Save current BIT RATE value
    *************************************************/

    #if defined __ADSPBF527__
        BMODE8_1:
        R6 = 0x8 (z); /* ADSP-BF527: BMODE [3:0] = 1000 - Boot from UART1 host (slave mode) */
        CC = R6 == R7;
        if !CC jump BMODE7_1;
        call _GET_UART_BITRATE;
        jump DPM;
    #endif

    BMODE7_1:
    R6 = 0x7 (z); /* ADSP-BF527: BMODE [3:0] = 0111 - Boot from UART0 host (slave mode) */
                  /* ADSP-BF537: BMODE [2:0] =  111 - Boot from UART0 host (slave mode) */
    CC = R6 == R7;
    if !CC jump DPM;
    call _GET_UART_BITRATE;

#endif /* defined (__ADSPBF527__) || defined (__ADSPBF537__) */


DPM: nop;
/*****************************************************************************************
 Description:   Dynamic Power Managment

 Important Notice:
 Depending on increasing/decreasing speed (core clock (CCLK) and/or system clock (SCLK)),
 the order of the registers PLL_CTL, PLL_DIV (and VR_CTL) have to be adapted!
 - Increase speed: 1.  VR_CTL, 2. PLL_DIV, 3. PLL_CTL
 - Decrease speed: 1. PLL_CTL, 2. PLL_DIV, 3.  VR_CTL
 If SDRAM is in use, the value for RDIV in the EBIU_SDRRC register has to be re-calculated
*****************************************************************************************/

/**************************
* PLL Lock Count Register *
**************************/

P5.H = hi(PLL_LOCKCNT);
P5.L = lo(PLL_LOCKCNT);

R7.L = PLL_LOCKCNT_VAL;
w[P5] = R7.L;


/*****************************************************************************
 Description:   Configure Voltage Regulator Control Register

 IMPORTANT
   NOTICE:      The same value should not be written twice
                to the VR_CTL register
******************************************************************************/

R6 = w[P5 + VR_CTL - PLL_LOCKCNT] (z);
R7 = VR_CTL_VAL (z);
CC = R6 == R7;
if CC jump skip_vr_ctl;

CLI R6;                             /* disable interrupts */
w[P5 + VR_CTL - PLL_LOCKCNT] = R7;  /* Apply VR_CTL changes */
IDLE;                               /* drain pipeline and send core into IDLE. Required for changing voltage settings */
STI R6;                             /* re-enable interrupts after wakeup */

skip_vr_ctl: nop;


/*********************************
* PLL Divide Register            *
* Can be configured on the fly   *
* First configure divider,       *
* than configure MSEL in PLL_CTL *
*********************************/

R7.L = PLL_DIV_VAL;
w[P5 + PLL_DIV - PLL_LOCKCNT] = R7;


/*****************************************************************************
 Description:   Configure PLL Control Register
 IMPORTANT
   NOTICE:      The same value should not be written twice
                to the PLL_CTL register
 IMPORTANT
   NOTICE
 for BF561:     Core B must be in idle state during this programming sequence
******************************************************************************/

R6 = w[P5 + PLL_CTL - PLL_LOCKCNT] (z);
R7 = PLL_CTL_VAL (z);
CC = R6 == R7;
if CC jump skip_pll_ctl;

CLI R6;                             /* disable interrupts */
w[P5 + PLL_CTL - PLL_LOCKCNT] = R7; /* Apply PLL_CTL changes */
IDLE;                               /* drain pipeline and send core into IDLE. Required for changing voltage settings */
STI R6;                             /* re-enable interrupts after wakeup */

skip_pll_ctl: nop;


/*************************************************
 Test for Boot Modes that reuqire special actions
*************************************************/

#if defined (__ADSPBF527__) || defined (__ADSPBF537__)

    P5.H = hi(SYSCR);
    P5.L = lo(SYSCR);

    R7 = w[P5] (z);
    #if defined __ADSPBF527__
        R6 = 0xF (z); /* BMODE [3:0] */
    #elif defined __ADSPBF537__
        R6 = 0x7 (z); /* BMODE [2:0] */
    #endif
    R7 = R6 & R7;

    /*************************************************
     UART Host Boot mode: Save current BIT RATE value
    *************************************************/

    #if defined __ADSPBF527__
        BMODE8_2:
        R6 = 0x8 (z); /* ADSP-BF527: BMODE [3:0] = 1000 - Boot from UART1 host (slave mode) */
        CC = R6 == R7;
        if !CC jump BMODE7_2;
        call _SET_UART_BITRATE;
        jump EBIU;
    #endif

    BMODE7_2:
    R6 = 0x7 (z); /* ADSP-BF527: BMODE [3:0] = 0111 - Boot from UART0 host (slave mode) */
                  /* ADSP-BF537: BMODE [2:0] =  111 - Boot from UART0 host (slave mode) */
    CC = R6 == R7;
    if !CC jump EBIU;
    call _SET_UART_BITRATE;

#endif /* defined (__ADSPBF527__) || defined (__ADSPBF537__) */


EBIU: nop;
/*****************************************************************************
 Description:   Configure EBIU
******************************************************************************/


/*****************************************************************************
 Description:   Configure and enable asynchronous memory
******************************************************************************/


/**********************************************
* Asynchronous Memory Bank Control 0 Register *
**********************************************/

P5.H = hi(EBIU_AMBCTL0);
P5.L = lo(EBIU_AMBCTL0);

IMM32(R7,EBIU_AMBCTL0_VAL);
[P5] = R7;


/**********************************************
* Asynchronous Memory Bank Control 1 Register *
**********************************************/

IMM32(R7,EBIU_AMBCTL1_VAL);
[P5 + EBIU_AMBCTL1 - EBIU_AMBCTL0] = R7;


/**********************************************
* Asynchronous Memory Global Control Register *
***********************************************/

R7.L = EBIU_AMGCTL_VAL;
w[P5 + EBIU_AMGCTL - EBIU_AMBCTL0] = R7;


/*****************************************************************************
 Description:   Configure and enable SDRAM
******************************************************************************/

#if defined WORKAROUND_05000070 /* see 'ezkitBF533_initcode.asm' for more details */
    P5.H = hi(EBIU_SDSTAT);
    P5.L = lo(EBIU_SDSTAT);
    R7.L = w[P5];
    CC = bittst(R7, bitpos(SDRS));
    if !CC jump skip_sdram_enable;
#endif


/*************************************
* SDRAM Memory Bank Control Register *
**************************************/

P5.H = hi(EBIU_SDBCTL);
P5.L = lo(EBIU_SDBCTL);

#if defined __ADSPBF561__
    IMM32(R7,EBIU_SDBCTL_VAL);
    [P5] = R7;
#else
    R7.L = EBIU_SDBCTL_VAL;
    w[P5] = R7.L;
#endif


/***************************************
* SDRAM Memory Global Control Register *
***************************************/

IMM32(R7,EBIU_SDGCTL_VAL);
[P5 + EBIU_SDGCTL - EBIU_SDBCTL] = R7;


#if defined WORKAROUND_05000070 /* see 'ezkitBF533_initcode.asm' for more details */
    skip_sdram_enable: nop;
#endif


/***************************************************************************
* SDRAM Refresh Rate Control Register                                      *
* RDIV has always to be re-calculated according to the actual system clock *
* You can either use the defined value that fits to the PCC settings or    *
* call _GET_RDIV to calculate RDIV 'on the fly'                            *
***************************************************************************/

call _GET_RDIV;
w[P5 + EBIU_SDRRC - EBIU_SDBCTL] = R0;


/*********************************************
* Restore System Interrupt Wakeup Registers  *
*********************************************/

P5.H = hi(SIC_IWR0);
P5.L = lo(SIC_IWR0);

R7 = -1;

[P5] = R7;
#if defined (__ADSPBF527__) || defined (__ADSPBF561__)
    [P5 + SIC_IWR1 - SIC_IWR0] = R7;
#endif


/*****************************************************************************
 Post-Init Section
 Restore all saved registers from stack
******************************************************************************/

(R7:0,P5:5) = [SP++];
ASTAT = [SP++];
unlink;
RTS;

_initcode.end:


/*****************************************************************************
 EBIU
*****************************************************************************/

/*****************************************************************************
 Prototypes
******************************************************************************/

//.GLOBAL _GET_RDIV;


/*****************************************************************************
 Functions
******************************************************************************/

.section L1_code;


/****************************************************************************
 Name:          _GET_RDIV
 
 Description:   Calculate RDIV value for SDRAM Refresh Rate Control Register
                RDIV = ( ( SCLK[MHz] * tREF[ms] ) / NRA ) - ( tRAS + tRP ) [clock cycles]
                RDIV = ( ( SCLK * 10^6 * 1/s * tREF * 10^-3 s ) / NRA ) - ( tRAS + tRP ) [clock cycles]
                SCLK = ( CLKIN * MSEL ) / SSEL = VCO / SSEL
                VCO = _GET_VCO_Hz
                SCLK = _GET_SCLK_Hz
                MSEL = Extracted from PLL_CTL register
                SSEL = Extracted from PLL_DIV register
                tREF = Definition
                NRA  = Definition
                tRAS = Extracted from EBIU_SDGCTL
                tRP = Extracted from EBIU_SDGCTL