ezkitbf561_initcode.h

关于bf531的好程序

/****************************************************************************
 Include Section
*****************************************************************************/


#include <Blackfin.h>
#include "..\nBlackfin.h"


/****************************************************************************
 System MMR Register Map
****************************************************************************/

/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SYSCR                   SICA_SYSCR          /* System Reset Configuration register for Core A */
#define SIC_IWR0                SICA_IWR0           /* SIC Interrupt Wakeup-Enable register 0 */
#define SIC_IWR1                SICA_IWR1           /* SIC Interrupt Wakeup-Enable register 1 */


/****************************************************************************
 Additional macro defines to enable the programmer to use symbolic names for
 register-access and bit-manipulation that are missed in 'defBF561.h'
****************************************************************************/

/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#ifndef SET_MSEL(x)
#define SET_MSEL(x)             (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
#endif

/* PLL_DIV Macros */
#ifndef SET_SSEL(x)
#define SET_SSEL(x)             ((x)&0xF)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
#endif

/* PLL_STAT Macros */
#ifndef VSTAT
#define VSTAT                   0x0010              /* Voltage Regulator Status: Regulator at programmed voltage */
#define CORE_IDLE               0x0040              /* processor is in the IDLE operating mode */
#define PLL_LOCKED              0x0020              /* PLL_LOCKCNT Has Been Reached */
#define SLEEP                   0x0010              /* processor is in the Sleep operating mode */
#define DEEP_SLEEP              0x0008              /* processor is in the Deep Sleep operating mode */
#define ACTIVE_PLLDISABLED      0x0004              /* Processor In Active Mode With PLL Disabled */
#define FULL_ON                 0x0002              /* Processor In Full On Mode */
#define ACTIVE_PLLENABLED       0x0001              /* Processor In Active Mode With PLL Enabled */
#endif

/* VR_CTL Masks */
#ifndef FREQ
#define FREQ                    0x0003              /* Switching Oscillator Frequency For Regulator */
#define FREQ_333                0x0001              /* Switching Frequency Is 333 kHz */
#define FREQ_667                0x0002              /* Switching Frequency Is 667 kHz */
#define FREQ_1000               0x0003              /* Switching Frequency Is 1 MHz */
#endif

#ifndef HIBERNATE
#define HIBERNATE               0x0000              /* Powerdown/Bypass On-Board Regulation */
#endif

#ifndef GAIN
#define GAIN                    0x000C              /* Voltage Level Gain	*/
#define GAIN_5                  0x0000              /* GAIN = 5 */
#define GAIN_10                 0x0004              /* GAIN = 10 */
#define GAIN_20                 0x0008              /* GAIN = 20 */
#define GAIN_50                 0x000C              /* GAIN = 50 */
#endif

#ifndef VLEV
#define VLEV                    0x00F0              /* Internal Voltage Level */
#define VLEV_085                0x0060              /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090                0x0070              /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095                0x0080              /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100                0x0090              /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105                0x00A0              /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110                0x00B0              /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115                0x00C0              /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120                0x00D0              /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125                0x00E0              /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130                0x00F0              /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#endif


/* **********************  SDRAM CONTROLLER MASKS  *************************** */
/* EBIU_SDGCTL Masks */
#ifndef PASR_ALL
#define PASR_ALL                0x00000000          /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR_B0_B1              0x00000010          /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
#define PASR_B0                 0x00000020          /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
#endif


/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
/* EBIU_AMGCTL Masks */
#ifndef CDPRIO
#define CDPRIO                  0x0100              /* DMA has priority over core for for external accesses */
#endif


/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
#ifndef PLL_WAKEUP_IRQ
#define PLL_WAKEUP_IRQ          0x00000001          /* PLL Wakeup Interrupt Request */
#endif


/*****************************************************************************
 Dynamic Power Managment
*****************************************************************************/


/********************************
* PLL Control Register Value    *
* Reset = 0x1400                *
* ADSP-BF561 EZ-KIT Lite:       *
* CLKIN = 30MHz                 *
* MSEL = 17                     *
* --> VCO = 30MHz x 17 = 510MHz *
********************************/

#define PLL_CTL_VAL             (\
                               nBYPASS          |   /* Bypass the PLL */\
                               nOUT_DELAY       |   /* Add 200ps Delay To EBIU Output Signals */\
                               nIN_DELAY        |   /* Add 200ps Delay To EBIU Input Latches */\
                               nPDWN            |   /* Enter Deep Sleep Mode */\
                               nSTOPCK          |   /* Core Clock Off */\
                               nPLL_OFF         |   /* PLL Not Powered */\
                               nPLL_CLKIN_DIV2  |   /* Pass CLKIN/2 to PLL */\
                                SET_MSEL(17)    |   /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */\
                                0)

#define CLKIN_MHz               30                  /* CLKIN [MHz] */
#define CLKIN_Hz                30000000            /* CLKIN [Hz] */
#define CLKIN                   CLKIN_MHz           /* CLKIN [MHz] */

#define VCO_MAX_MHz             600                 /* VCO [MHz] */
#define VCO_MAX_Hz              600000000           /* VCO [Hz] */
#define VCO_MAX                 VCO_MAX_MHz         /* VCO [MHz] */


/***********************************
* PLL Divide Register Value        *
* Reset = 0x0005                   *
* ADSP-BF561 EZ-KIT Lite:          *
* CSEL = 1                         *
* --> CCLK = VCO / CSEL            *
* --> CCLK = 510MHz / 1 = 510MHz   *
* SSEL = 4                         *
* --> SCLK = VCO / SSEL            *
* --> SCLK = 510MHz / 4 = 127.5MHz *
***********************************/

#define PLL_DIV_VAL             (\
                                SET_SSEL(4)     |   /* Set SSEL = 1-15 --> SCLK = VCO/SSEL */\
                                CCLK_DIV1       |   /* CCLK = VCO / 1 */\
                                0)

#define CCLK_MAX_MHz            VCO_MAX_MHz         /* Maximum Core Clock [MHz] */
#define CCLK_MAX_Hz             VCO_MAX_Hz          /* Maximum Core Clock [Hz] */
#define CCLK_MAX                CCLK_MAX_MHz        /* Maximum Core Clock [MHz] */

#define SCLK_MAX_MHz            133                 /* Maximum System Clock [MHz] */
#define SCLK_MAX_Hz             133000000           /* Maximum System Clock [Hz] */
#define SCLK_MAX                SCLK_MAX_MHz        /* Maximum System Clock [MHz] */


/********************************
* PLL Lock Count Register Value *
* Reset = 0x0200                *
********************************/

#define PLL_LOCKCNT_VAL         0x0200