macros.h

关于bf531的好程序

/*****************************************************************************
 Symbolic constants & definitions
******************************************************************************/

#define CORE_MMR_BASE   0xFFE00000
#define SYS_MMR_BASE    0xFFC00000


/*****************************************************************************
 macros
******************************************************************************/

#define INIT_MACROS\
    P5.H = hi(SMMR_BASE);\
    P5.L = lo(SMMR_BASE);\
    P4.H = hi(CMMR_BASE);\
    P4.L = lo(CMMR_BASE)

/* data register 32-bit write access */
#define LOAD32(reg,val) reg##.H=hi(val); reg##.L=lo(val)
#define IMM32(reg,val)  reg##.H=hi(val); reg=lo(val)

/* data register 16-bit write access */
#define LOAD16(reg,val)\
    reg = val(z)

/* system MMR 32-bit read access */
#define LOAD32_SMMR(dreg,smmr)\
    dreg = [P5 + smmr - SMMR_BASE]

/* system MMR 16-bit read access */
#define LOAD16_SMMR(dreg,smmr)\
    dreg = w[P5 + smmr - SMMR_BASE]

/* system MMR 32-bit write access */
#define STORE32_SMMR(smmr,dreg)\
    [P5 + smmr - SMMR_BASE] = dreg

#define STORE32im_SMMR(smmr,val)\
    R7.H = hi(val);\
    R7.L = lo(val);\
    [P5 + smmr - SMMR_BASE] = R7


/* system MMR 16-bit write access */
#define STORE16_SMMR(smmr,dreg)\
    w[P5 + smmr - SMMR_BASE] = dreg

#define STORE16im_SMMR(smmr,val)\
    R7.L = val;\
    w[P5 + smmr - SMMR_BASE] = R7


/* All core MMRs must be accessed with a 32-bit read or write access */
#define LOAD_CMMR(dreg,cmmr)\
    dreg = [P5 + cmmr - CMMR_BASE]

#define STORE_CMMR(cmmr,dreg)\
    [P5 + cmmr - SMMR_BASE] = dreg

















#define PUSH_DAG_REGx(x)\
    [--SP] = I ## x;\
    [--SP] = B ## x;\
    [--SP] = M ## x;\
    [--SP] = L ## x


#define PUSH_DAG_REG\
    [--SP] = I0;\
    [--SP] = B0;\
    [--SP] = M0;\
    [--SP] = L0;\
    [--SP] = I1;\
    [--SP] = B1;\
    [--SP] = M1;\
    [--SP] = L1;\
    [--SP] = I2;\
    [--SP] = B2;\
    [--SP] = M2;\
    [--SP] = L2;\
    [--SP] = I3;\
    [--SP] = B3;\
    [--SP] = M3;\
    [--SP] = L


#define POP_DAG_REGx(x)\
    L ## x = [SP++];\
    M ## x = [SP++];\
    B ## x = [SP++];\
    I ## x = [SP++]


#define POP_DAG_REG\
    L3 = [SP++];\
    M3 = [SP++];\
    B3 = [SP++];\
    I3 = [SP++];\
    L2 = [SP++];\
    M2 = [SP++];\
    B2 = [SP++];\
    I2 = [SP++];\
    L1 = [SP++];\
    M1 = [SP++];\
    B1 = [SP++];\
    I1 = [SP++];\
    L0 = [SP++];\
    M0 = [SP++];\
    B0 = [SP++];\
    I0 = [SP++]


/* 
 * Set the corresponding bits in a System Register (SR); 
 * All bits set in "mask" will be set in the system register 
 * specified by "sys_reg" bitset_SR(sys_reg, mask), where 
 * sys_reg is the system register and mask are the bits to be set. 
 */
#define bitset_SR(sys_reg, mask)\
        [--SP] = (R7:6);\
        R7 = sys_reg;\
        R6.H = (mask) >> 16;\
        R6.L = (mask) & 0xffff;\
        R7 = R7 | R6;\
        sys_reg = R7;\
        CSYNC;\
        (R7:6) = [SP++]

/* 
 * Clear the corresponding bits in a System Register (SR); 
 * All bits set in "mask" will be cleared in the SR 
 * specified by "sys_reg" bitclr_SR(sys_reg, mask), where 
 * sys_reg is the SR and mask are the bits to be cleared. 
 */
#define bitclr_SR(sys_reg, mask)\
        [--SP] = (R7:6);\
        R7 = sys_reg;\
        R7 =~ R7;\
        R6.L = (mask) & 0xffff;\
        R6.H = (mask) >> 16;\
        R7 = R7 | R6;\
        R7 =~ R7;\
        sys_reg = R7;\
        CSYNC;\
        (R7:6) = [SP++]

/* 
 * Set the corresponding bits in a Memory Mapped Register (MMR); 
 * All bits set in "mask" will be set in the MMR specified by "mmr_reg"
 * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are 
 * the bits to be set. 
 */
#define bitset_MMR(mmr_reg, mask)\
        [--SP] = (R7:6);\
        [--SP] = P5;\
        P5.L = mmr_reg & 0xffff;\
        P5.H = mmr_reg >> 16;\
        R7 = [P5];\
        R6.L = (mask) & 0xffff;\
        R6.H = (mask) >> 16;\
        R7 = R7 | R6;\
        [P5] = R7;\
        CSYNC;\
        P5 = [SP++];\
        (R7:6) = [SP++]

/* 
 * Clear the corresponding bits in a Memory Mapped Register (MMR); 
 * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
 * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are 
 * the bits to be cleared. 
 */
#define bitclr_MMR(mmr_reg, mask)\
        [--SP] = (R7:6);\
        [--SP] = P5;\
        P5.L = mmr_reg & 0xffff;\
        P5.H = mmr_reg >> 16;\
        R7 = [P5];\
        R7 =~ R7;\
        R6.L = (mask) & 0xffff;\
        R6.H = (mask) >> 16;\
        R7 = R7 | R6;\
        R7 =~ R7;\
        [P5] = R7;\
        CSYNC;\
        P5 = [SP++];\
        (R7:6) = [SP++]