mux_rab.tdf

用于测试VGA运行的几个程序代码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 4.1 cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 2 
SUBDESIGN mux_rab
( 
	data[3..0]	:	input;
	result[0..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data23w[3..0]	: WIRE;
	w_result24w	: WIRE;
	w_result37w	: WIRE;
	w_result38w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result24w);
	sel_node[] = ( sel[1..0]);
	w_data23w[] = ( data[3..0]);
	w_result24w = w_result37w;
	w_result37w = (((w_data23w[1..1] & sel_node[0..0]) & (! w_result38w)) # (w_result38w & (w_data23w[3..3] # (! sel_node[0..0]))));
	w_result38w = (((w_data23w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data23w[2..2])));
END;
--VALID FILE