vgainterface.map.rpt

用于测试VGA运行的几个程序代码

; |vgainterface                            ; 101 (97)    ; 51           ; 16384       ; 8    ; 0            ; 50 (48)      ; 31 (29)           ; 20 (20)          ; 24 (24)         ; |vgainterface                                                                                        ;
;    |tsinghua:u1|                         ; 4 (0)       ; 2            ; 16384       ; 0    ; 0            ; 2 (0)        ; 2 (0)             ; 0 (0)            ; 0 (0)           ; |vgainterface|tsinghua:u1                                                                            ;
;       |altsyncram:altsyncram_component|  ; 4 (0)       ; 2            ; 16384       ; 0    ; 0            ; 2 (0)        ; 2 (0)             ; 0 (0)            ; 0 (0)           ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component                                            ;
;          |altsyncram_qcr:auto_generated| ; 4 (2)       ; 2            ; 16384       ; 0    ; 0            ; 2 (0)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated              ;
;             |mux_rab:mux2|               ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2 ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/VGA_example/VGA_example/VGA_test2/vgainterface/vgainterface.map.eqn.


+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                    ;
+-------------------------------------------------------------------------+-----------------+
; File Name                                                               ; Used in Netlist ;
+-------------------------------------------------------------------------+-----------------+
; vgainterface.vhd                                                        ; yes             ;
; E:/VGA_example/VGA_example/VGA_test2/vgainterface/tsinghua.vhd          ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf              ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/stratix_ram_block.inc       ; yes             ;
; E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/altsyncram_qcr.tdf ; yes             ;
; E:/VGA_example/VGA_example/VGA_test2/vgainterface/db/mux_rab.tdf        ; yes             ;
+-------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 101     ;
; Total combinational functions     ; 70      ;
; Total 4-input functions           ; 32      ;
; Total 3-input functions           ; 6       ;
; Total 2-input functions           ; 8       ;
; Total 1-input functions           ; 24      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 51      ;
; Total logic cells in carry chains ; 24      ;
; I/O pins                          ; 8       ;
; Total memory bits                 ; 16384   ;
; Maximum fan-out node              ; reset   ;
; Maximum fan-out                   ; 49      ;
; Total fan-out                     ; 421     ;
; Average fan-out                   ; 3.73    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                          ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+
; Name                                                                                 ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF              ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+
; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 16384        ; 1            ; --           ; --           ; 16384 ; vgainterface.mif ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 24    ;
; Number of synthesis-generated cells                    ; 77    ;
; Number of WYSIWYG LUTs                                 ; 24    ;
; Number of synthesis-generated LUTs                     ; 46    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 51    ;
; Number of cells with combinational logic only          ; 50    ;
; Number of cells with registers only                    ; 31    ;
; Number of cells with combinational logic and registers ; 20    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 49    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jul 05 12:38:44 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off vgainterface -c vgainterface
Info: Found 2 design units, including 1 entities, in source file vgainterface.vhd
    Info: Found design unit 1: vgainterface-vgainterface
    Info: Found entity 1: vgainterface
Info: Using design file tsinghua.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: tsinghua-SYN
    Info: Found entity 1: tsinghua
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qcr.tdf
    Info: Found entity 1: altsyncram_qcr
Info: Found 1 design units, including 1 entities, in source file db/mux_rab.tdf
    Info: Found entity 1: mux_rab
Info: Implemented 113 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 5 output pins
    Info: Implemented 101 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jul 05 12:38:49 2005
    Info: Elapsed time: 00:00:04