vgainterface.tan.qmsg

用于测试VGA运行的几个程序代码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] vga_blue clock0 2.243 ns " "Info: Found hold time violation between source  pin or register tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] and destination pin or register vga_blue for clock clock0 (Hold time is 2.243 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.399 ns + Largest " "Info: + Largest clock skew is 3.399 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 destination 12.035 ns + Longest register " "Info: + Longest clock path from clock clock0 to destination register is 12.035 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.921 ns) + CELL(0.720 ns) 8.776 ns clock_25mhz 2 REG LC_X11_Y6_N2 44 " "Info: 2: + IC(6.921 ns) + CELL(0.720 ns) = 8.776 ns; Loc. = LC_X11_Y6_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.641 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.712 ns) + CELL(0.547 ns) 12.035 ns vga_blue 3 REG LC_X15_Y6_N1 1 " "Info: 3: + IC(2.712 ns) + CELL(0.547 ns) = 12.035 ns; Loc. = LC_X15_Y6_N1; Fanout = 1; REG Node = 'vga_blue'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.259 ns" { clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.96 % " "Info: Total cell delay = 2.402 ns ( 19.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.633 ns 80.04 % " "Info: Total interconnect delay = 9.633 ns ( 80.04 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.035 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 8.636 ns - Shortest register " "Info: - Shortest clock path from clock clock0 to source register is 8.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.954 ns) + CELL(0.547 ns) 8.636 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 2 REG LC_X15_Y6_N4 2 " "Info: 2: + IC(6.954 ns) + CELL(0.547 ns) = 8.636 ns; Loc. = LC_X15_Y6_N4; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.501 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 19.48 % " "Info: Total cell delay = 1.682 ns ( 19.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.954 ns 80.52 % " "Info: Total interconnect delay = 6.954 ns ( 80.52 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.636 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.035 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.636 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.995 ns - Shortest register register " "Info: - Shortest register to register delay is 0.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 1 REG LC_X15_Y6_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y6_N4; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38 2 COMB LC_X15_Y6_N4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X15_Y6_N4; Fanout = 2; COMB Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.291 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/mux_rab.tdf" "" "" { Text "F:/program_test/vgainterface/db/mux_rab.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.368 ns) 0.995 ns vga_blue 3 REG LC_X15_Y6_N1 1 " "Info: 3: + IC(0.336 ns) + CELL(0.368 ns) = 0.995 ns; Loc. = LC_X15_Y6_N1; Fanout = 1; REG Node = 'vga_blue'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.704 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.659 ns 66.23 % " "Info: Total cell delay = 0.659 ns ( 66.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.336 ns 33.77 % " "Info: Total interconnect delay = 0.336 ns ( 33.77 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.995 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.035 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.636 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.995 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock0 vga_vs_control vga_vs_control~reg0 15.485 ns register " "Info: tco from clock clock0 to destination pin vga_vs_control through register vga_vs_control~reg0 is 15.485 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.003 ns + Longest register " "Info: + Longest clock path from clock clock0 to source register is 12.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.921 ns) + CELL(0.720 ns) 8.776 ns clock_25mhz 2 REG LC_X11_Y6_N2 44 " "Info: 2: + IC(6.921 ns) + CELL(0.720 ns) = 8.776 ns; Loc. = LC_X11_Y6_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.641 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.680 ns) + CELL(0.547 ns) 12.003 ns vga_vs_control~reg0 3 REG LC_X10_Y8_N6 1 " "Info: 3: + IC(2.680 ns) + CELL(0.547 ns) = 12.003 ns; Loc. = LC_X10_Y8_N6; Fanout = 1; REG Node = 'vga_vs_control~reg0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.227 ns" { clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 20.01 % " "Info: Total cell delay = 2.402 ns ( 20.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.601 ns 79.99 % " "Info: Total interconnect delay = 9.601 ns ( 79.99 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.309 ns + Longest register pin " "Info: + Longest register to pin delay is 3.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_vs_control~reg0 1 REG LC_X10_Y8_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N6; Fanout = 1; REG Node = 'vga_vs_control~reg0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.687 ns) + CELL(1.622 ns) 3.309 ns vga_vs_control 2 PIN PIN_140 0 " "Info: 2: + IC(1.687 ns) + CELL(1.622 ns) = 3.309 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'vga_vs_control'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.309 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 49.02 % " "Info: Total cell delay = 1.622 ns ( 49.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.687 ns 50.98 % " "Info: Total interconnect delay = 1.687 ns ( 50.98 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.309 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz vga_vs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.309 ns" { vga_vs_control~reg0 vga_vs_control } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock0 vga_read_dispaly vga_read_dispaly~reg0 15.166 ns register " "Info: Minimum tco from clock clock0 to destination pin vga_read_dispaly through register vga_read_dispaly~reg0 is 15.166 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.003 ns + Shortest register " "Info: + Shortest clock path from clock clock0 to source register is 12.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.921 ns) + CELL(0.720 ns) 8.776 ns clock_25mhz 2 REG LC_X11_Y6_N2 44 " "Info: 2: + IC(6.921 ns) + CELL(0.720 ns) = 8.776 ns; Loc. = LC_X11_Y6_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.641 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.680 ns) + CELL(0.547 ns) 12.003 ns vga_read_dispaly~reg0 3 REG LC_X10_Y8_N7 1 " "Info: 3: + IC(2.680 ns) + CELL(0.547 ns) = 12.003 ns; Loc. = LC_X10_Y8_N7; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.227 ns" { clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 20.01 % " "Info: Total cell delay = 2.402 ns ( 20.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.601 ns 79.99 % " "Info: Total interconnect delay = 9.601 ns ( 79.99 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.990 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_read_dispaly~reg0 1 REG LC_X10_Y8_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N7; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.368 ns) + CELL(1.622 ns) 2.990 ns vga_read_dispaly 2 PIN PIN_131 0 " "Info: 2: + IC(1.368 ns) + CELL(1.622 ns) = 2.990 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'vga_read_dispaly'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.990 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 54.25 % " "Info: Total cell delay = 1.622 ns ( 54.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.368 ns 45.75 % " "Info: Total interconnect delay = 1.368 ns ( 45.75 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.990 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.990 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 26 16:34:22 2005 " "Info: Processing ended: Tue Apr 26 16:34:22 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}