vgainterface.tan.qmsg

用于测试VGA运行的几个程序代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_25mhz " "Info: Detected ripple clock clock_25mhz as buffer" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 67 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock_25mhz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock0 register address\[8\] memory tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8 184.5 MHz 5.42 ns Internal " "Info: Clock clock0 has Internal fmax of 184.5 MHz between source register address\[8\] and destination memory tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8 (period= 5.42 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.788 ns + Longest register memory " "Info: + Longest register to memory delay is 1.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[8\] 1 REG LC_X12_Y6_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y6_N7; Fanout = 4; REG Node = 'address\[8\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { address[8] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 217 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.493 ns) + CELL(0.295 ns) 1.788 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8 2 MEM M4K_X13_Y5 1 " "Info: 2: + IC(1.493 ns) + CELL(0.295 ns) = 1.788 ns; Loc. = M4K_X13_Y5; Fanout = 1; MEM Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.788 ns" { address[8] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.295 ns 16.50 % " "Info: Total cell delay = 0.295 ns ( 16.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.493 ns 83.50 % " "Info: Total interconnect delay = 1.493 ns ( 83.50 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.788 ns" { address[8] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.387 ns - Smallest " "Info: - Smallest clock skew is -3.387 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 destination 8.616 ns + Shortest memory " "Info: + Shortest clock path from clock clock0 to destination memory is 8.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.925 ns) + CELL(0.556 ns) 8.616 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8 2 MEM M4K_X13_Y5 1 " "Info: 2: + IC(6.925 ns) + CELL(0.556 ns) = 8.616 ns; Loc. = M4K_X13_Y5; Fanout = 1; MEM Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg8'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.481 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.691 ns 19.63 % " "Info: Total cell delay = 1.691 ns ( 19.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.925 ns 80.37 % " "Info: Total interconnect delay = 6.925 ns ( 80.37 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.616 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.003 ns - Longest register " "Info: - Longest clock path from clock clock0 to source register is 12.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.921 ns) + CELL(0.720 ns) 8.776 ns clock_25mhz 2 REG LC_X11_Y6_N2 44 " "Info: 2: + IC(6.921 ns) + CELL(0.720 ns) = 8.776 ns; Loc. = LC_X11_Y6_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.641 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.680 ns) + CELL(0.547 ns) 12.003 ns address\[8\] 3 REG LC_X12_Y6_N7 4 " "Info: 3: + IC(2.680 ns) + CELL(0.547 ns) = 12.003 ns; Loc. = LC_X12_Y6_N7; Fanout = 4; REG Node = 'address\[8\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.227 ns" { clock_25mhz address[8] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 217 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 20.01 % " "Info: Total cell delay = 2.402 ns ( 20.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.601 ns 79.99 % " "Info: Total interconnect delay = 9.601 ns ( 79.99 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz address[8] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.616 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz address[8] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 217 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/VGA_test2/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.788 ns" { address[8] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.616 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg8 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.003 ns" { clock0 clock_25mhz address[8] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock2 register count_z\[0\] register count_z\[1\] 399.36 MHz 2.504 ns Internal " "Info: Clock clock2 has Internal fmax of 399.36 MHz between source register count_z\[0\] and destination register count_z\[1\] (period= 2.504 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.302 ns + Longest register register " "Info: + Longest register to register delay is 2.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_z\[0\] 1 REG LC_X16_Y6_N6 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N6; Fanout = 9; REG Node = 'count_z\[0\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { count_z[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.597 ns) + CELL(0.333 ns) 0.930 ns add~45COUT1 2 COMB LC_X16_Y6_N0 2 " "Info: 2: + IC(0.597 ns) + CELL(0.333 ns) = 0.930 ns; Loc. = LC_X16_Y6_N0; Fanout = 2; COMB Node = 'add~45COUT1'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.930 ns" { count_z[0] add~45COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.398 ns add~46 3 COMB LC_X16_Y6_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.468 ns) = 1.398 ns; Loc. = LC_X16_Y6_N1; Fanout = 1; COMB Node = 'add~46'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.468 ns" { add~45COUT1 add~46 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.568 ns) 2.302 ns count_z\[1\] 4 REG LC_X16_Y6_N7 12 " "Info: 4: + IC(0.336 ns) + CELL(0.568 ns) = 2.302 ns; Loc. = LC_X16_Y6_N7; Fanout = 12; REG Node = 'count_z\[1\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.904 ns" { add~46 count_z[1] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns 59.47 % " "Info: Total cell delay = 1.369 ns ( 59.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.933 ns 40.53 % " "Info: Total interconnect delay = 0.933 ns ( 40.53 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.302 ns" { count_z[0] add~45COUT1 add~46 count_z[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock2 destination 8.365 ns + Shortest register " "Info: + Shortest clock path from clock clock2 to destination register is 8.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock2 1 CLK PIN_124 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_124; Fanout = 5; CLK Node = 'clock2'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock2 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.683 ns) + CELL(0.547 ns) 8.365 ns count_z\[1\] 2 REG LC_X16_Y6_N7 12 " "Info: 2: + IC(6.683 ns) + CELL(0.547 ns) = 8.365 ns; Loc. = LC_X16_Y6_N7; Fanout = 12; REG Node = 'count_z\[1\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.230 ns" { clock2 count_z[1] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 20.11 % " "Info: Total cell delay = 1.682 ns ( 20.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.683 ns 79.89 % " "Info: Total interconnect delay = 6.683 ns ( 79.89 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock2 source 8.365 ns - Longest register " "Info: - Longest clock path from clock clock2 to source register is 8.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock2 1 CLK PIN_124 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_124; Fanout = 5; CLK Node = 'clock2'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock2 } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.683 ns) + CELL(0.547 ns) 8.365 ns count_z\[0\] 2 REG LC_X16_Y6_N6 9 " "Info: 2: + IC(6.683 ns) + CELL(0.547 ns) = 8.365 ns; Loc. = LC_X16_Y6_N6; Fanout = 9; REG Node = 'count_z\[0\]'" {  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.230 ns" { clock2 count_z[0] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 20.11 % " "Info: Total cell delay = 1.682 ns ( 20.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.683 ns 79.89 % " "Info: Total interconnect delay = 6.683 ns ( 79.89 % )" {  } {  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[1] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0}  } { { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.302 ns" { count_z[0] add~45COUT1 add~46 count_z[1] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[1] } "NODE_NAME" } } } { "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/VGA_test2/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/VGA_test2/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.365 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock0 6 " "Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock clock0 with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}