vgainterface.tan.qmsg

用于测试VGA运行的几个程序代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 26 16:34:21 2005 " "Info: Processing started: Tue Apr 26 16:34:21 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off vgainterface -c vgainterface --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off vgainterface -c vgainterface --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock0 " "Info: Assuming node clock0 is an undefined clock" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 9 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock2 " "Info: Assuming node clock2 is an undefined clock" {  } { { "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/VGA_test2/vgainterface/vgainterface.vhd" 10 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock2" } } } }  } 0}  } {  } 0}