vgainterface.map.eqn

用于测试VGA运行的几个程序代码

--A1L321Q is vga_hs_control~reg0
--operation mode is normal

A1L321Q_lut_out = vga_h_sync;
A1L321Q = DFFEA(A1L321Q_lut_out, clock_25mhz, reset, , , , );


--A1L031Q is vga_vs_control~reg0
--operation mode is normal

A1L031Q_lut_out = vga_v_sync;
A1L031Q = DFFEA(A1L031Q_lut_out, clock_25mhz, reset, , , , );


--A1L621Q is vga_read_dispaly~reg0
--operation mode is normal

A1L621Q_lut_out = vga_h_sync & vga_v_sync & vga_read;
A1L621Q = DFFEA(A1L621Q_lut_out, clock_25mhz, reset, , , , );


--A1L911Q is vga_green_dispaly~reg0
--operation mode is normal

A1L911Q_lut_out = vga_h_sync & vga_v_sync & vga_green;
A1L911Q = DFFEA(A1L911Q_lut_out, clock_25mhz, reset, , , , );


--A1L211Q is vga_blue_dispaly~reg0
--operation mode is normal

A1L211Q_lut_out = vga_h_sync & vga_v_sync & vga_blue;
A1L211Q = DFFEA(A1L211Q_lut_out, clock_25mhz, reset, , , , );


--vga_h_sync is vga_h_sync
--operation mode is normal

vga_h_sync_lut_out = !count_x[8] & !count_x[7] # !count_x[9];
vga_h_sync = DFFEA(vga_h_sync_lut_out, clock_25mhz, reset, , , , );


--clock_25mhz is clock_25mhz
--operation mode is normal

clock_25mhz_lut_out = !clock_25mhz;
clock_25mhz = DFFEA(clock_25mhz_lut_out, clock0, reset, , , , );


--vga_v_sync is vga_v_sync
--operation mode is normal

vga_v_sync_lut_out = !A1L501;
vga_v_sync = DFFEA(vga_v_sync_lut_out, clock_25mhz, reset, , , , );


--vga_read is vga_read
--operation mode is normal

vga_read_lut_out = A1L021 & !A1L69 & (count_z[4] # !A1L89);
vga_read = DFFEA(vga_read_lut_out, clock_25mhz, reset, , A1L721, , );


--vga_green is vga_green
--operation mode is normal

vga_green_lut_out = A1L021 & (count_z[4] # A1L301 # !count_z[3]);
vga_green = DFFEA(vga_green_lut_out, clock_25mhz, reset, , A1L721, , );


--vga_blue is vga_blue
--operation mode is normal

vga_blue_lut_out = E1L2 & A1L3 & (A1L411 # A1L611);
vga_blue = DFFEA(vga_blue_lut_out, clock_25mhz, reset, , A1L721, , );


--count_x[8] is count_x[8]
--operation mode is normal

count_x[8]_lut_out = A1L63 & !A1L801;
count_x[8] = DFFEA(count_x[8]_lut_out, clock_25mhz, reset, , , , );


--count_x[7] is count_x[7]
--operation mode is normal

count_x[7]_lut_out = A1L43;
count_x[7] = DFFEA(count_x[7]_lut_out, clock_25mhz, reset, , , , );


--count_x[9] is count_x[9]
--operation mode is normal

count_x[9]_lut_out = A1L83 & !A1L801;
count_x[9] = DFFEA(count_x[9]_lut_out, clock_25mhz, reset, , , , );


--count_y[8] is count_y[8]
--operation mode is normal

count_y[8]_lut_out = A1L55 & (!count_y[1] # !A1L001 # !A1L501);
count_y[8] = DFFEA(count_y[8]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[7] is count_y[7]
--operation mode is normal

count_y[7]_lut_out = A1L35 & (!count_y[1] # !A1L001 # !A1L501);
count_y[7] = DFFEA(count_y[7]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[6] is count_y[6]
--operation mode is normal

count_y[6]_lut_out = A1L15 & (!count_y[1] # !A1L001 # !A1L501);
count_y[6] = DFFEA(count_y[6]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[5] is count_y[5]
--operation mode is normal

count_y[5]_lut_out = A1L94 & (!count_y[1] # !A1L001 # !A1L501);
count_y[5] = DFFEA(count_y[5]_lut_out, clock_25mhz, reset, , A1L801, , );


--A1L501 is reduce_nor~108
--operation mode is normal

A1L501 = count_y[8] & count_y[7] & count_y[6] & count_y[5];


--D1_ram_block1a1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a1_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a1_PORT_A_address_reg = DFFE(D1_ram_block1a1_PORT_A_address, D1_ram_block1a1_clock_0, , , );
D1_ram_block1a1_clock_0 = clock0;
D1_ram_block1a1_PORT_A_data_out = MEMORY(, , D1_ram_block1a1_PORT_A_address_reg, , , , , , D1_ram_block1a1_clock_0, , , , , );
D1_ram_block1a1 = D1_ram_block1a1_PORT_A_data_out[0];


--D1_address_reg_a[0] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0]
--operation mode is normal

D1_address_reg_a[0]_lut_out = address[12];
D1_address_reg_a[0] = DFFEA(D1_address_reg_a[0]_lut_out, clock0, VCC, , , , );


--D1_ram_block1a2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a2_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a2_PORT_A_address_reg = DFFE(D1_ram_block1a2_PORT_A_address, D1_ram_block1a2_clock_0, , , );
D1_ram_block1a2_clock_0 = clock0;
D1_ram_block1a2_PORT_A_data_out = MEMORY(, , D1_ram_block1a2_PORT_A_address_reg, , , , , , D1_ram_block1a2_clock_0, , , , , );
D1_ram_block1a2 = D1_ram_block1a2_PORT_A_data_out[0];


--D1_address_reg_a[1] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[1]
--operation mode is normal

D1_address_reg_a[1]_lut_out = address[13];
D1_address_reg_a[1] = DFFEA(D1_address_reg_a[1]_lut_out, clock0, VCC, , , , );


--D1_ram_block1a0 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a0_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a0_PORT_A_address_reg = DFFE(D1_ram_block1a0_PORT_A_address, D1_ram_block1a0_clock_0, , , );
D1_ram_block1a0_clock_0 = clock0;
D1_ram_block1a0_PORT_A_data_out = MEMORY(, , D1_ram_block1a0_PORT_A_address_reg, , , , , , D1_ram_block1a0_clock_0, , , , , );
D1_ram_block1a0 = D1_ram_block1a0_PORT_A_data_out[0];


--E1L1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~37
--operation mode is normal

E1L1 = D1_address_reg_a[1] & (D1_address_reg_a[0] # D1_ram_block1a2) # !D1_address_reg_a[1] & !D1_address_reg_a[0] & D1_ram_block1a0;


--D1_ram_block1a3 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a3_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a3_PORT_A_address_reg = DFFE(D1_ram_block1a3_PORT_A_address, D1_ram_block1a3_clock_0, , , );
D1_ram_block1a3_clock_0 = clock0;
D1_ram_block1a3_PORT_A_data_out = MEMORY(, , D1_ram_block1a3_PORT_A_address_reg, , , , , , D1_ram_block1a3_clock_0, , , , , );
D1_ram_block1a3 = D1_ram_block1a3_PORT_A_data_out[0];


--E1L2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38
--operation mode is normal

E1L2 = E1L1 & (D1_ram_block1a3 # !D1_address_reg_a[0]) # !E1L1 & D1_ram_block1a1 & D1_address_reg_a[0];


--count_x[6] is count_x[6]
--operation mode is normal

count_x[6]_lut_out = A1L23;
count_x[6] = DFFEA(count_x[6]_lut_out, clock_25mhz, reset, , , , );


--A1L3 is address[0]~148
--operation mode is normal

A1L3 = !count_x[9] & (!count_x[6] # !count_x[7] # !count_x[8]);


--count_z[2] is count_z[2]
--operation mode is normal

count_z[2]_lut_out = A1L06 & (count_z[1] # !A1L401 # !count_z[4]);
count_z[2] = DFFEA(count_z[2]_lut_out, clock2, reset, , , , );


--count_z[3] is count_z[3]
--operation mode is normal

count_z[3]_lut_out = A1L26;
count_z[3] = DFFEA(count_z[3]_lut_out, clock2, reset, , , , );


--count_z[4] is count_z[4]
--operation mode is normal

count_z[4]_lut_out = A1L46 & (count_z[1] # !A1L401 # !count_z[4]);
count_z[4] = DFFEA(count_z[4]_lut_out, clock2, reset, , , , );


--count_z[1] is count_z[1]
--operation mode is normal

count_z[1]_lut_out = A1L85 & (count_z[1] # !A1L401 # !count_z[4]);
count_z[1] = DFFEA(count_z[1]_lut_out, clock2, reset, , , , );


--count_z[0] is count_z[0]
--operation mode is normal

count_z[0]_lut_out = A1L65;
count_z[0] = DFFEA(count_z[0]_lut_out, clock2, reset, , , , );


--A1L79 is process10~310
--operation mode is normal

A1L79 = count_z[3] # count_z[4] # !count_z[1] & !count_z[0];


--A1L021 is vga_green~124
--operation mode is normal

A1L021 = E1L2 & A1L3 & (count_z[2] # A1L79);


--A1L89 is process10~311
--operation mode is normal

A1L89 = count_z[2] & count_z[0] & count_z[1] & !count_z[3] # !count_z[2] & !count_z[1] & count_z[3];


--A1L99 is process10~312
--operation mode is normal

A1L99 = !count_z[3] & !count_z[4];


--A1L69 is process10~94
--operation mode is normal

A1L69 = count_z[2] & A1L99 & (!count_z[0] # !count_z[1]);


--count_y[4] is count_y[4]
--operation mode is normal

count_y[4]_lut_out = A1L74;
count_y[4] = DFFEA(count_y[4]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[3] is count_y[3]
--operation mode is normal

count_y[3]_lut_out = A1L54;
count_y[3] = DFFEA(count_y[3]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[2] is count_y[2]
--operation mode is normal

count_y[2]_lut_out = A1L34;
count_y[2] = DFFEA(count_y[2]_lut_out, clock_25mhz, reset, , A1L801, , );


--count_y[0] is count_y[0]
--operation mode is normal

count_y[0]_lut_out = A1L93 & (!count_y[1] # !A1L001 # !A1L501);
count_y[0] = DFFEA(count_y[0]_lut_out, clock_25mhz, reset, , A1L801, , );


--A1L001 is process10~313
--operation mode is normal

A1L001 = !count_y[4] & !count_y[3] & !count_y[2] & !count_y[0];


--count_y[1] is count_y[1]
--operation mode is normal

count_y[1]_lut_out = A1L14 & (!count_y[1] # !A1L001 # !A1L501);
count_y[1] = DFFEA(count_y[1]_lut_out, clock_25mhz, reset, , A1L801, , );


--A1L101 is process10~314
--operation mode is normal

A1L101 = !count_y[8] & !count_y[6] & !count_y[5] & !count_y[1];


--A1L201 is process10~315
--operation mode is normal

A1L201 = A1L001 & (A1L101 # count_y[8] $ !count_y[7]) # !A1L001 & (count_y[8] $ !count_y[7]);


--A1L721 is vga_read~4
--operation mode is normal

A1L721 = !count_x[9] & !A1L201;


--A1L301 is process10~316
--operation mode is normal

A1L301 = !count_z[2] & !count_z[1];


--A1L311 is vga_blue~497
--operation mode is normal

A1L311 = count_z[2] & (count_z[0] # count_z[1]) # !count_z[2] & !count_z[1] # !count_z[3];


--A1L411 is vga_blue~498
--operation mode is normal

A1L411 = A1L311 & !count_z[4] & !A1L69;


--A1L511 is vga_blue~499
--operation mode is normal

A1L511 = count_z[2] # count_z[3] # count_z[1] & count_z[0];


--A1L611 is vga_blue~500
--operation mode is normal

A1L611 = count_z[4] & (A1L511 # !count_z[2] & !A1L79) # !count_z[4] & !count_z[2] & !A1L79;


--A1L63 is add~34
--operation mode is arithmetic

A1L63_carry_eqn = A1L53;
A1L63 = count_x[8] $ !A1L63_carry_eqn;

--A1L73 is add~34COUT
--operation mode is arithmetic

A1L73 = CARRY(count_x[8] & !A1L53);


--A1L601 is reduce_nor~109
--operation mode is normal

A1L601 = count_x[7] # count_x[6] # !count_x[8] # !count_x[9];


--count_x[5] is count_x[5]
--operation mode is normal

count_x[5]_lut_out = A1L03 & !A1L801;
count_x[5] = DFFEA(count_x[5]_lut_out, clock_25mhz, reset, , , , );


--count_x[4] is count_x[4]
--operation mode is normal

count_x[4]_lut_out = A1L82;
count_x[4] = DFFEA(count_x[4]_lut_out, clock_25mhz, reset, , , , );


--count_x[3] is count_x[3]
--operation mode is normal

count_x[3]_lut_out = A1L62;
count_x[3] = DFFEA(count_x[3]_lut_out, clock_25mhz, reset, , , , );


--count_x[2] is count_x[2]
--operation mode is normal

count_x[2]_lut_out = A1L42;
count_x[2] = DFFEA(count_x[2]_lut_out, clock_25mhz, reset, , , , );


--A1L701 is reduce_nor~110
--operation mode is normal

A1L701 = count_x[5] # !count_x[2] # !count_x[3] # !count_x[4];


--count_x[1] is count_x[1]
--operation mode is normal

count_x[1]_lut_out = A1L22;
count_x[1] = DFFEA(count_x[1]_lut_out, clock_25mhz, reset, , , , );


--count_x[0] is count_x[0]
--operation mode is normal

count_x[0]_lut_out = A1L02;
count_x[0] = DFFEA(count_x[0]_lut_out, clock_25mhz, reset, , , , );


--A1L801 is reduce_nor~111