vgainterface.tan.qmsg

用于测试VGA运行的几个程序代码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] vga_blue clock0 2.692 ns " "Info: Found hold time violation between source  pin or register tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] and destination pin or register vga_blue for clock clock0 (Hold time is 2.692 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.522 ns + Largest " "Info: + Largest clock skew is 3.522 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 destination 12.125 ns + Longest register " "Info: + Longest clock path from clock clock0 to destination register is 12.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X8_Y10_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X8_Y10_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.781 ns) + CELL(0.547 ns) 12.125 ns vga_blue 3 REG LC_X12_Y8_N1 1 " "Info: 3: + IC(2.781 ns) + CELL(0.547 ns) = 12.125 ns; Loc. = LC_X12_Y8_N1; Fanout = 1; REG Node = 'vga_blue'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.328 ns" { clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.81 % " "Info: Total cell delay = 2.402 ns ( 19.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.723 ns 80.19 % " "Info: Total interconnect delay = 9.723 ns ( 80.19 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.125 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 8.603 ns - Shortest register " "Info: - Shortest clock path from clock clock0 to source register is 8.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.921 ns) + CELL(0.547 ns) 8.603 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 2 REG LC_X12_Y8_N0 2 " "Info: 2: + IC(6.921 ns) + CELL(0.547 ns) = 8.603 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.468 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 19.55 % " "Info: Total cell delay = 1.682 ns ( 19.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.921 ns 80.45 % " "Info: Total interconnect delay = 6.921 ns ( 80.45 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.603 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.125 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.603 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.669 ns - Shortest register register " "Info: - Shortest register to register delay is 0.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\] 1 REG LC_X12_Y8_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; REG Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|address_reg_a\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 40 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38 2 COMB LC_X12_Y8_N0 2 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; COMB Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|mux_rab:mux2\|w_result37w~38'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.291 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/mux_rab.tdf" "" "" { Text "F:/program_test/vgainterface/db/mux_rab.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.238 ns) 0.669 ns vga_blue 3 REG LC_X12_Y8_N1 1 " "Info: 3: + IC(0.140 ns) + CELL(0.238 ns) = 0.669 ns; Loc. = LC_X12_Y8_N1; Fanout = 1; REG Node = 'vga_blue'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.378 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.529 ns 79.07 % " "Info: Total cell delay = 0.529 ns ( 79.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.140 ns 20.93 % " "Info: Total interconnect delay = 0.140 ns ( 20.93 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.669 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 168 -1 0 } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.125 ns" { clock0 clock_25mhz vga_blue } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.603 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.669 ns" { tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 vga_blue } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock0 vga_hs_control vga_hs_control~reg0 15.264 ns register " "Info: tco from clock clock0 to destination pin vga_hs_control through register vga_hs_control~reg0 is 15.264 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.146 ns + Longest register " "Info: + Longest clock path from clock clock0 to source register is 12.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X8_Y10_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X8_Y10_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.802 ns) + CELL(0.547 ns) 12.146 ns vga_hs_control~reg0 3 REG LC_X10_Y11_N8 1 " "Info: 3: + IC(2.802 ns) + CELL(0.547 ns) = 12.146 ns; Loc. = LC_X10_Y11_N8; Fanout = 1; REG Node = 'vga_hs_control~reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.349 ns" { clock_25mhz vga_hs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.78 % " "Info: Total cell delay = 2.402 ns ( 19.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.744 ns 80.22 % " "Info: Total interconnect delay = 9.744 ns ( 80.22 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.146 ns" { clock0 clock_25mhz vga_hs_control~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.945 ns + Longest register pin " "Info: + Longest register to pin delay is 2.945 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_hs_control~reg0 1 REG LC_X10_Y11_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N8; Fanout = 1; REG Node = 'vga_hs_control~reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_hs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(1.622 ns) 2.945 ns vga_hs_control 2 PIN PIN_139 0 " "Info: 2: + IC(1.323 ns) + CELL(1.622 ns) = 2.945 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'vga_hs_control'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.945 ns" { vga_hs_control~reg0 vga_hs_control } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 55.08 % " "Info: Total cell delay = 1.622 ns ( 55.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.323 ns 44.92 % " "Info: Total interconnect delay = 1.323 ns ( 44.92 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.945 ns" { vga_hs_control~reg0 vga_hs_control } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.146 ns" { clock0 clock_25mhz vga_hs_control~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.945 ns" { vga_hs_control~reg0 vga_hs_control } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock0 vga_read_dispaly vga_read_dispaly~reg0 15.010 ns register " "Info: Minimum tco from clock clock0 to destination pin vga_read_dispaly through register vga_read_dispaly~reg0 is 15.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.146 ns + Shortest register " "Info: + Shortest clock path from clock clock0 to source register is 12.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X8_Y10_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X8_Y10_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.802 ns) + CELL(0.547 ns) 12.146 ns vga_read_dispaly~reg0 3 REG LC_X10_Y11_N2 1 " "Info: 3: + IC(2.802 ns) + CELL(0.547 ns) = 12.146 ns; Loc. = LC_X10_Y11_N2; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.349 ns" { clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.78 % " "Info: Total cell delay = 2.402 ns ( 19.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.744 ns 80.22 % " "Info: Total interconnect delay = 9.744 ns ( 80.22 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.146 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.691 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_read_dispaly~reg0 1 REG LC_X10_Y11_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N2; Fanout = 1; REG Node = 'vga_read_dispaly~reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 141 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(1.622 ns) 2.691 ns vga_read_dispaly 2 PIN PIN_131 0 " "Info: 2: + IC(1.069 ns) + CELL(1.622 ns) = 2.691 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'vga_read_dispaly'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.691 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 60.27 % " "Info: Total cell delay = 1.622 ns ( 60.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.069 ns 39.73 % " "Info: Total interconnect delay = 1.069 ns ( 39.73 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.691 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.146 ns" { clock0 clock_25mhz vga_read_dispaly~reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "2.691 ns" { vga_read_dispaly~reg0 vga_read_dispaly } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 25 15:28:10 2005 " "Info: Processing ended: Mon Apr 25 15:28:10 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}