📄 class.ptf
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#
# This class.ptf file built by Component Editor
# 2006.07.15.21:16:36
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
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# DO NOT MODIFY THIS FILE
#
CLASS isp1362
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
type = "verilog";
filepath = "hdl/ISP1362_IF.v";
}
}
top_module_name = "ISP1362_IF.v:ISP1362_IF";
emit_system_h = "0";
LIBRARIES
{
}
}
MODULE_DEFAULTS global_signals
{
class = "isp1362";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Has_Clock = "1";
Top_Level_Ports_Are_Enumerated = "1";
}
COMPONENT_BUILDER
{
GLS_SETTINGS
{
}
}
PORT_WIRING
{
PORT iCLK
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
hdl_parameters
{
}
}
SIMULATION
{
DISPLAY
{
}
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Group = "1";
Has_Clock = "0";
Address_Width = "2";
Address_Alignment = "native";
Data_Width = "16";
Has_Base_Address = "1";
Has_IRQ = "1";
Setup_Time = "100ns";
Hold_Time = "100ns";
Read_Wait_States = "100ns";
Write_Wait_States = "100ns";
Read_Latency = "0";
Maximum_Pending_Read_Transactions = "0";
Active_CS_Through_Read_Latency = "0";
Is_Printable_Device = "0";
Is_Memory_Device = "0";
Is_Readable = "1";
Is_Writable = "1";
Minimum_Uninterrupted_Run_Length = "1";
}
COMPONENT_BUILDER
{
AVS_SETTINGS
{
Setup_Value = "100";
Read_Wait_Value = "100";
Write_Wait_Value = "100";
Hold_Value = "100";
Timing_Units = "ns";
Read_Latency_Value = "0";
Minimum_Arbitration_Shares = "1";
Active_CS_Through_Read_Latency = "0";
Max_Pending_Read_Transactions_Value = "1";
Address_Alignment = "native";
Is_Printable_Device = "0";
Interleave_Bursts = "0";
interface_name = "Avalon Slave";
external_wait = "0";
Is_Memory_Device = "0";
}
}
PORT_WIRING
{
PORT iDATA
{
width = "16";
width_expression = "";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iADDR
{
width = "2";
width_expression = "";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iRD_N
{
width = "1";
width_expression = "";
direction = "input";
type = "read_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iWR_N
{
width = "1";
width_expression = "";
direction = "input";
type = "write_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iCS_N
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT iRST_N
{
width = "1";
width_expression = "";
direction = "input";
type = "reset_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oDATA
{
width = "16";
width_expression = "";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT oINT0_N
{
width = "1";
width_expression = "";
direction = "output";
type = "irq_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_DATA
{
width = "16";
width_expression = "";
direction = "inout";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_ADDR
{
width = "2";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_RD_N
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_WR_N
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_CS_N
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_RST_N
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_INT0
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT OTG_INT1
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
SLAVE avalon_slave_1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Group = "2";
Has_Clock = "0";
Address_Width = "0";
Address_Alignment = "native";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "1";
Setup_Time = "0ns";
Hold_Time = "0ns";
Read_Wait_States = "1ns";
Write_Wait_States = "1ns";
Read_Latency = "0";
Maximum_Pending_Read_Transactions = "0";
Active_CS_Through_Read_Latency = "0";
Is_Printable_Device = "0";
Is_Memory_Device = "0";
Is_Readable = "0";
Is_Writable = "0";
Minimum_Uninterrupted_Run_Length = "1";
}
COMPONENT_BUILDER
{
AVS_SETTINGS
{
Setup_Value = "0";
Read_Wait_Value = "1";
Write_Wait_Value = "1";
Hold_Value = "0";
Timing_Units = "ns";
Read_Latency_Value = "0";
Minimum_Arbitration_Shares = "1";
Active_CS_Through_Read_Latency = "0";
Max_Pending_Read_Transactions_Value = "1";
Address_Alignment = "native";
Is_Printable_Device = "0";
Interleave_Bursts = "0";
interface_name = "Avalon Slave";
external_wait = "0";
Is_Memory_Device = "0";
}
}
PORT_WIRING
{
PORT oINT1_N
{
width = "1";
width_expression = "";
direction = "output";
type = "irq_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
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