cpu_rom.txt

有C编写的红绿灯的控制

-- Behavioural model of a 256-word, 8-bit Read Only Memory
-- download from: www.fpga.com.cn & www.pld.com.cn

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.cpu8pac.ALL;
ENTITY rom256x8 IS
        PORT(address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             csbar, oebar : IN STD_LOGIC;
             data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rom256x8;

--version 1 loads acca and accb from locations 254 and 256
--and exclusive or's the values and jumps back to repeat
ARCHITECTURE version1 OF rom256x8 IS   
        TYPE rom_array IS ARRAY (0 TO 255) OF BIT_VECTOR(7 DOWNTO 0);
        CONSTANT rom_values : rom_array := 
                        (0 => clra & X"0",
                         1 => lda & X"0",    --lda $FE
                         2 => X"fe",
                         3 => ldb & X"0",    --ldb $FF
                         4 => X"ff",
                         5 => lxor & X"0",   --lxor
                         6 => jmp & X"0",    --jmp $001
                         7 => X"01",
                         254 => X"aa",
                         255 => X"55",
                         OTHERS => X"00");
BEGIN
PROCESS(address, csbar, oebar)
        VARIABLE index : INTEGER := 0;
BEGIN
        IF (csbar = '1' OR oebar = '1') 
                THEN data <= "ZZZZZZZZ";
        ELSE

                --calculate address as an integer
                index := 0;
                FOR i IN address'RANGE LOOP
                        IF address(i) = '1' THEN
                        index := index + 2**i;
                        END IF;
                END LOOP;

                --assign to output data lines
                data <= To_StdlogicVector(rom_values(index));

        END IF;
END PROCESS;
END version1;

--version2 increments a location in the ram
-- download from: www.fpga.com.cn & www.pld.com.cn

ARCHITECTURE version2 OF rom256x8 IS   
        TYPE rom_array IS ARRAY (0 TO 255) OF BIT_VECTOR(7 DOWNTO 0);
        CONSTANT rom_values : rom_array := 
                        (0 => clra & X"0",
                         1 => sta & X"1",    --sta $100
                         2 => X"00",
                         3 => lda & X"1",    --lda $100
                         4 => X"00",
                         5 => inc & X"0",   --inc a
                         6 => jmp & X"0",    --jmp $001
                         7 => X"01",
                         OTHERS => X"00");
BEGIN
PROCESS(address, csbar, oebar)
        VARIABLE index : INTEGER := 0;
BEGIN
        IF (csbar = '1' OR oebar = '1') 
                THEN data <= "ZZZZZZZZ";
        ELSE

                --calculate address as an integer
                index := 0;
                FOR i IN address'RANGE LOOP
                        IF address(i) = '1' THEN
                        index := index + 2**i;
                        END IF;
                END LOOP;

                --assign to output data lines
                data <= To_StdlogicVector(rom_values(index));

        END IF;
END PROCESS;
END version2;