priority_encoder_ls.vhd

有C编写的红绿灯的控制

-----------------------------------------------------------------------------
--
--      The following information has been generated by Exemplar Logic and
--      may be freely distributed and modified.
--
--      Entity name : priority_encoder
--
--      Purpose : This design is an n-bit priority encoder. It looks at the 
--        input data bus and returns the address of the 1st "1" found in the
--        word. If also has a output the detects if the entire data bus is all
--        zeros.
--	download from: www.pld.com.cn & www.fpga.com.cn 
----------------------------------------------------------------------------
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;

entity priority_encoder is
   generic (data_width    : natural := 25 ;
            address_width : natural := 5 ) ;
   port (
         data    : in  UNSIGNED(data_width - 1 downto 0) ;
         address : out UNSIGNED(address_width - 1 downto 0) ;
         none    : out STD_LOGIC
        );
end priority_encoder ;

architecture rtl of priority_encoder is
  attribute SYNTHESIS_RETURN : STRING ;
  
  FUNCTION to_stdlogic (arg1:BOOLEAN)  RETURN STD_LOGIC IS
      BEGIN
      IF(arg1) THEN
        RETURN('1') ;
      ELSE
        RETURN('0') ;
      END IF ;
  END ;

    function to_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
	variable result: UNSIGNED(SIZE-1 downto 0);
	variable temp: integer;
        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
    begin
	temp := ARG;
	for i in 0 to SIZE-1 loop
	    if (temp mod 2) = 1 then
		result(i) := '1';
	    else 
		result(i) := '0';
	    end if;
	    if temp > 0 then
		temp := temp / 2;
	    else
		temp := (temp - 1) / 2; 
	    end if;
	end loop;
	return result;
    end;

  constant zero : UNSIGNED(data_width downto 1) := (others => '0') ;
  begin
PRIO :  process(data)
         variable temp_address : UNSIGNED(address_width - 1 downto 0) ;
         begin
          temp_address := (others => '0') ;
          for i in data_width - 1 downto 0 loop
            if (data(i) = '1') then
              temp_address := to_unsigned(i,address_width) ;
              exit ;
            end if ;
          end loop ;
          address <= temp_address ;
          none <= to_stdlogic(data = zero) ;
        end process ;
end RTL ;