📄 ytc01.lst
字号:
__start:
__text_start:
0013 E5CF LDI R28,0x5F
0014 E0D2 LDI R29,2
0015 BFCD OUT 0x3D,R28
0016 BFDE OUT 0x3E,R29
0017 51C0 SUBI R28,0x10
0018 40D0 SBCI R29,0
0019 EA0A LDI R16,0xAA
001A 8308 STD Y+0,R16
001B 2400 CLR R0
001C E6E3 LDI R30,0x63
001D E0F0 LDI R31,0
001E E010 LDI R17,0
001F 39E5 CPI R30,0x95
0020 07F1 CPC R31,R17
0021 F011 BEQ 0x0024
0022 9201 ST R0,Z+
0023 CFFB RJMP 0x001F
0024 8300 STD Z+0,R16
0025 E2E2 LDI R30,0x22
0026 E0F0 LDI R31,0
0027 E6A0 LDI R26,0x60
0028 E0B0 LDI R27,0
0029 E010 LDI R17,0
002A 32E5 CPI R30,0x25
002B 07F1 CPC R31,R17
002C F021 BEQ 0x0031
002D 95C8 LPM
002E 9631 ADIW R30,1
002F 920D ST R0,X+
0030 CFF9 RJMP 0x002A
0031 D12D RCALL _main
_exit:
0032 CFFF RJMP _exit
FILE: E:\job\elite\云台控制器\avr\ytcpg01.c
(0001) //update on 2004-04-22 21:45
(0002) //chage Level check : DBNEW
(0003) // deal with rotory speed unsteable
(0004)
(0005)
(0006) //one charter a to send
(0007) #include <iom8515v.h>
(0008) #include <macros.h>
(0009) #include <eeprom.h>
(0010)
(0011) //outport define
(0012) #define OUTau8ON PORTC|=0x01
(0013) #define OUTau8OFF PORTC&=~0x01
(0014) #define OUTau7ON PORTC|=0x02
(0015) #define OUTau7OFF PORTC&=~0x02
(0016) #define OUTau6ON PORTC|=0x04
(0017) #define OUTau6OFF PORTC&=~0x04
(0018) #define OUTau5ON PORTC|=0x08
(0019) #define OUTau5OFF PORTC&=~0x08
(0020) #define OUTau4ON PORTC|=0x10
(0021) #define OUTau4OFF PORTC&=~0x10
(0022) #define OUTau3ON PORTC|=0x20
(0023) #define OUTau3OFF PORTC&=~0x20
(0024) #define OUTau2ON PORTC|=0x40
(0025) #define OUTau2OFF PORTC&=~0x40
(0026) #define OUTau1ON PORTC|=0x80
(0027) #define OUTau1OFF PORTC&=~0x80
(0028) #define OUTau1Pulse PORTC^=0x80
(0029)
(0030) #define CLROFF PORTB|=0x01
(0031) #define CLRON PORTB&=~0x01
(0032)
(0033) #define BOARDID '1'
(0034)
(0035) //全局变量
(0036) unsigned char OPDATA[12];
(0037)
(0038)
(0039) unsigned char TXbuf[18];
(0040) unsigned char RXbuf[18];
(0041) unsigned char tmpRx=0;
(0042) unsigned char RXCR=0;
(0043) unsigned char RXstartFlag=0;
(0044)
(0045) union mdd {
(0046) unsigned int TXCRC;
(0047) unsigned char txCRC[2];
(0048) }CRCT;
(0049)
(0050) void watchdog_init(void)
(0051) {
(0052) WDR();
_watchdog_init:
0033 95A8 WDR
(0053) WDTCR=0x0F ;
0034 E08F LDI R24,0xF
0035 BD81 OUT 0x21,R24
0036 9508 RET
(0054) }
(0055)
(0056) void Delay_1ms(void)
(0057) {
(0058) unsigned int i;
(0059)
(0060) for (i = 1; i<1140; i++)
_Delay_1ms:
i --> R16
0037 E001 LDI R16,1
0038 E010 LDI R17,0
0039 C002 RJMP 0x003C
003A 5F0F SUBI R16,0xFF
003B 4F1F SBCI R17,0xFF
003C 3704 CPI R16,0x74
003D E0E4 LDI R30,4
003E 071E CPC R17,R30
003F F3D0 BCS 0x003A
0040 9508 RET
_delayXms:
i --> R20
n --> R22
0041 D159 RCALL push_gset2
0042 01B8 MOVW R22,R16
(0061)
(0062) ;
(0063) }
(0064)
(0065) void delayXms(unsigned int n)
(0066) {
(0067) unsigned int i=0;
0043 2744 CLR R20
0044 2755 CLR R21
0045 C003 RJMP 0x0049
(0068) while(i<n)
(0069) {
(0070) Delay_1ms();
0046 DFF0 RCALL _Delay_1ms
(0071) i++;
0047 5F4F SUBI R20,0xFF
0048 4F5F SBCI R21,0xFF
0049 1746 CP R20,R22
004A 0757 CPC R21,R23
004B F3D0 BCS 0x0046
004C D135 RCALL pop_gset2
004D 9508 RET
(0072) }
(0073) }
(0074)
(0075) void port_init(void)
(0076) {
(0077) PORTA=0xF0; //PA set to 1
_port_init:
004E EF80 LDI R24,0xF0
004F BB8B OUT 0x1B,R24
(0078) DDRA=0xF0; //PA0-PA3:ADC PA4-PA6:KL0-KL2(OUT)
0050 BB8A OUT 0x1A,R24
(0079) //PA7:LCD-E (OUTPUT)
(0080)
(0081) PORTB=0xFF; //PB set to 1
0051 EF8F LDI R24,0xFF
0052 BB88 OUT 0x18,R24
(0082) DDRB=0xFF; //PB0-PB2:QN0-QN2 PB3:TEMPC(OUT)
0053 BB87 OUT 0x17,R24
(0083) //PB4-PB7:KR0-KR3(IN)
(0084)
(0085) PORTC=0x00; //PC set to 1
0054 2422 CLR R2
0055 BA25 OUT 0x15,R2
(0086) DDRC=0xFF; //PC0-PC7:DB0-DB7
0056 BB84 OUT 0x14,R24
(0087)
(0088) PORTD=0x00; //PD set to 1
0057 BA22 OUT 0x12,R2
(0089) DDRD=0x02;
0058 E082 LDI R24,2
0059 BB81 OUT 0x11,R24
(0090) //OUTDEON;
(0091)
(0092) SFIOR&=~(1<<PUD); //OPEN UP LINK
005A B780 IN R24,0x30
005B 7F8B ANDI R24,0xFB
005C BF80 OUT 0x30,R24
005D 9508 RET
(0093)
(0094) //delayXms(2000); //delay 1s
(0095) }
(0096)
(0097) void SPI_MasterInit(void)
(0098) {
(0099) //SPCR=0xD1; //SPIE ,SPE ,Master enable ;1/16 Fcl
(0100) SPCR=0x51; // ,SPE ,Master enable ;1/16 Fcl
_SPI_MasterInit:
005E E581 LDI R24,0x51
005F B98D OUT 0x0D,R24
0060 9508 RET
(0101) }
(0102) void SPI_Tran(void)
(0103) {
(0104) unsigned char i;
(0105) for(i=8;i>0;i--)
_SPI_Tran:
i --> R16
0061 E008 LDI R16,0x8
0062 C00B RJMP 0x006E
(0106) {
(0107) SPDR=OPDATA[i];
0063 E889 LDI R24,0x89
0064 E090 LDI R25,0
0065 2FE0 MOV R30,R16
0066 27FF CLR R31
0067 0FE8 ADD R30,R24
0068 1FF9 ADC R31,R25
0069 8020 LDD R2,Z+0
006A B82F OUT 0x0F,R2
(0108) while(!(SPSR&0x80));
006B 9B77 SBIS 0x0E,7
006C CFFE RJMP 0x006B
006D 950A DEC R16
006E 2422 CLR R2
006F 1620 CP R2,R16
0070 F390 BCS 0x0063
0071 9508 RET
(0109) }
(0110) //delayXms(1);
(0111)
(0112) }//unsigned
(0113)
(0114)
(0115)
(0116) void uart_init(void)
(0117) {
(0118) UCSRB=0x00;
_uart_init:
0072 2422 CLR R2
0073 B82A OUT 0x0A,R2
(0119) UBRR=0x33; //9600bps
0074 E383 LDI R24,0x33
0075 B989 OUT 0x09,R24
(0120) //UCR=0xd8;
(0121) UCSRB=(1<<RXCIE)|(1<<RXEN)|(1<<TXEN);
0076 E988 LDI R24,0x98
0077 B98A OUT 0x0A,R24
(0122) UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
0078 E886 LDI R24,0x86
0079 BD80 OUT 0x20,R24
007A 9508 RET
(0123) }
(0124)
(0125)
(0126) #pragma interrupt_handler uart0_tx_isr:12
(0127) void uart0_tx_isr(void)
(0128) {
(0129) ;
_uart0_tx_isr:
007B 9518 RETI
_uart0_rx_isr:
i --> R20
007C D121 RCALL push_lset
007D D106 RCALL push_gset1
(0130)
(0131) }
(0132)
(0133) #pragma interrupt_handler uart0_rx_isr:10
(0134) void uart0_rx_isr(void)
(0135) {
(0136)
(0137) unsigned char i;
(0138) //SEI();
(0139) tmpRx=UDR;
007E B02C IN R2,0x0C
007F 92200060 STS 0x60,R2
(0140) ////while(!(UCSRA & (1<<UDRE)))
(0141) //// ;
(0142) ////UDR=tmpRx; //TX the data of rx
(0143)
(0144) //OUTrunON;
(0145) if (tmpRx=='%')
0081 2D82 MOV R24,R2
0082 3285 CPI R24,0x25
0083 F431 BNE 0x008A
(0146) {
(0147)
(0148) //PORTC=0xff;
(0149) RXCR=0;
0084 2422 CLR R2
0085 92200061 STS 0x61,R2
(0150) RXstartFlag=1;
0087 E081 LDI R24,1
0088 93800062 STS 0x62,R24
(0151) }//if tmprx
(0152)
(0153) if (RXCR>16)
008A E180 LDI R24,0x10
008B 90200061 LDS R2,0x61
008D 1582 CP R24,R2
008E F418 BCC 0x0092
(0154) {
(0155) RXCR=0;
008F 2422 CLR R2
0090 92200061 STS 0x61,R2
(0156) //
(0157) }
(0158)
(0159) RXbuf[RXCR]=tmpRx;
0092 E685 LDI R24,0x65
0093 E090 LDI R25,0
0094 91E00061 LDS R30,0x61
0096 27FF CLR R31
0097 0FE8 ADD R30,R24
0098 1FF9 ADC R31,R25
0099 90200060 LDS R2,0x60
009B 8220 STD Z+0,R2
(0160) RXCR++;
009C 91800061 LDS R24,0x61
009E 5F8F SUBI R24,0xFF
009F 93800061 STS 0x61,R24
(0161) //SEI();
(0162)
(0163) if(RXstartFlag==1 && RXCR==15 && RXbuf[0]=='%')
00A1 91800062 LDS R24,0x62
00A3 3081 CPI R24,1
00A4 F009 BEQ 0x00A6
00A5 C072 RJMP 0x0118
00A6 91800061 LDS R24,0x61
00A8 308F CPI R24,0xF
00A9 F009 BEQ 0x00AB
00AA C06D RJMP 0x0118
00AB 91800065 LDS R24,_RXbuf
00AD 3285 CPI R24,0x25
00AE F009 BEQ 0x00B0
00AF C068 RJMP 0x0118
(0164) {
(0165) RXstartFlag=0;
00B0 2422 CLR R2
00B1 92200062 STS 0x62,R2
(0166) // OUTau1Pulse;
(0167) if(RXbuf[1]==BOARDID && RXbuf[14]=='$')
00B3 91800066 LDS R24,_RXbuf+1
00B5 3381 CPI R24,0x31
00B6 F009 BEQ 0x00B8
00B7 C059 RJMP 0x0111
00B8 91800073 LDS R24,0x73
00BA 3284 CPI R24,0x24
00BB F009 BEQ 0x00BD
00BC C054 RJMP 0x0111
(0168) //if(RXbuf[1]==BOARDID)
(0169) {
(0170) //OUTau1Pulse;
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