📄 m8m01.lst
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00D6 2628 EOR R2,R24
00D7 BA28 OUT 0x18,R2
00D8 9029 LD R2,Y+
00D9 BE2F OUT 0x3F,R2
00DA 91F9 LD R31,Y+
00DB 91E9 LD R30,Y+
00DC 9199 LD R25,Y+
00DD 9189 LD R24,Y+
00DE 9109 LD R16,Y+
00DF 9039 LD R3,Y+
00E0 9029 LD R2,Y+
00E1 9518 RETI
(0188)
(0189) }//void uart1_rx_isr(void)
(0190) void TXbufRDY(void)
(0191) {
(0192) TXBUF[0]=SlaveCR;
_TXbufRDY:
00E2 90200061 LDS R2,0x61
00E4 9220008C STS _TXBUF,R2
(0193) TXBUF[1]=SlaveCR;
00E6 9220008D STS _TXBUF+1,R2
(0194) TXBUF[2]=TRFG0;
00E8 EF8E LDI R24,0xFE
00E9 9380008E STS _TXBUF+2,R24
(0195) TXBUF[3]=TRFG1;
00EB EF8D LDI R24,0xFD
00EC 9380008F STS _TXBUF+3,R24
(0196) TXBUF[4]=SlaveCR;
00EE 92200090 STS 0x90,R2
(0197) TXBUF[5]=0xFF;
00F0 EF8F LDI R24,0xFF
00F1 93800091 STS 0x91,R24
(0198) TXBUF[12]=TRFG2;
00F3 EF81 LDI R24,0xF1
00F4 93800098 STS 0x98,R24
(0199) TXBUF[13]=TRFG3;
00F6 EF80 LDI R24,0xF0
00F7 93800099 STS 0x99,R24
00F9 9508 RET
(0200) }//void TXbufRDY(void)
(0201)
(0202) void RXBUFCLR(void)
(0203) {
(0204) unsigned char i=0;
_RXBUFCLR:
i --> R16
00FA 2700 CLR R16
(0205) for(i=0;i<RXINTMAX;i++)
00FB C009 RJMP 0x0105
(0206) RXBUF[i]=0;
00FC E68E LDI R24,0x6E
00FD E090 LDI R25,0
00FE 2FE0 MOV R30,R16
00FF 27FF CLR R31
0100 0FE8 ADD R30,R24
0101 1FF9 ADC R31,R25
0102 2422 CLR R2
0103 8220 STD Z+0,R2
0104 9503 INC R16
0105 90200064 LDS R2,0x64
0107 1502 CP R16,R2
0108 F398 BCS 0x00FC
0109 9508 RET
_RXRCK:
010A D0F3 RCALL push_gset2
(0207) }//void RXBUFCLR(void)
(0208)
(0209) void RXRCK(void) //检查收到的数据是否有效
(0210) {
(0211) if(RXbufP>RXbufPmax)
010B 90200069 LDS R2,0x69
010D 90300068 LDS R3,0x68
010F 1423 CP R2,R3
0110 F5B0 BCC 0x0147
(0212) {
(0213)
(0214) RXERROR=2;
0111 E082 LDI R24,2
0112 9380006A STS 0x6A,R24
(0215) if(RXBUF[12]==TRFG3 & RXBUF[11]==TRFG2 & RXBUF[1]==TRFG0 & RXBUF[2]==TRFG1)
0114 9180007A LDS R24,0x7A
0116 3F80 CPI R24,0xF0
0117 F419 BNE 0x011B
0118 E061 LDI R22,1
0119 E070 LDI R23,0
011A C002 RJMP 0x011D
011B 2766 CLR R22
011C 2777 CLR R23
011D 91800079 LDS R24,0x79
011F 3F81 CPI R24,0xF1
0120 F419 BNE 0x0124
0121 E041 LDI R20,1
0122 E050 LDI R21,0
0123 C002 RJMP 0x0126
0124 2744 CLR R20
0125 2755 CLR R21
0126 9180006F LDS R24,_RXBUF+1
0128 3F8E CPI R24,0xFE
0129 F419 BNE 0x012D
012A E021 LDI R18,1
012B E030 LDI R19,0
012C C002 RJMP 0x012F
012D 2722 CLR R18
012E 2733 CLR R19
012F 91800070 LDS R24,_RXBUF+2
0131 3F8D CPI R24,0xFD
0132 F419 BNE 0x0136
0133 E001 LDI R16,1
0134 E010 LDI R17,0
0135 C002 RJMP 0x0138
0136 2700 CLR R16
0137 2711 CLR R17
0138 011B MOVW R2,R22
0139 2224 AND R2,R20
013A 2235 AND R3,R21
013B 2222 AND R2,R18
013C 2233 AND R3,R19
013D 2220 AND R2,R16
013E 2231 AND R3,R17
013F 2022 TST R2
0140 F411 BNE 0x0143
0141 2033 TST R3
0142 F039 BEQ 0x014A
(0216) {
(0217)
(0218) RXERROR=0;
0143 2422 CLR R2
0144 9220006A STS 0x6A,R2
(0219) }
(0220)
(0221) }//if(RXbufP>RXbufPmax)
0146 C003 RJMP 0x014A
(0222) else
(0223) {
(0224) RXERROR=1;
0147 E081 LDI R24,1
0148 9380006A STS 0x6A,R24
(0225) }//else
(0226) if(RXERROR==0)
014A 9020006A LDS R2,0x6A
014C 2022 TST R2
014D F411 BNE 0x0150
(0227) {
(0228) OUTLED4ON;
014E 98C3 CBI 0x18,3
(0229) }
014F C001 RJMP 0x0151
(0230) else
(0231) {
(0232) OUTLED4OFF;
0150 9AC3 SBI 0x18,3
(0233) }
0151 D093 RCALL pop_gset2
0152 9508 RET
(0234) }//void RXRCK(void)
(0235)
(0236) unsigned char SLSTEP=10;
(0237) void main()
(0238) {
(0239) unsigned char i=0;
_main:
i --> R20
0153 2744 CLR R20
(0240)
(0241) //delayXms(500);
(0242) port_init(); //IO初始化
0154 DF19 RCALL _port_init
(0243) uart_init();
0155 DF28 RCALL _uart_init
(0244) //timer_init();
(0245) delayXms(10);
0156 E00A LDI R16,0xA
0157 E010 LDI R17,0
0158 DF08 RCALL _delayXms
(0246) SEI();
0159 9478 BSET 7
(0247) SLSTEP=10;
015A E08A LDI R24,0xA
015B 9380006D STS 0x6D,R24
(0248) for(i=0;i<17;i++)
015D C009 RJMP 0x0167
(0249) {
(0250) SlaveEN[i]=0xff;
015E E98C LDI R24,0x9C
015F E090 LDI R25,0
0160 2FE4 MOV R30,R20
0161 27FF CLR R31
0162 0FE8 ADD R30,R24
0163 1FF9 ADC R31,R25
0164 EF8F LDI R24,0xFF
0165 8380 STD Z+0,R24
0166 9543 INC R20
0167 3141 CPI R20,0x11
0168 F3A8 BCS 0x015E
(0251) }//for
(0252) SlaveCR=5;
0169 E085 LDI R24,5
016A 93800061 STS 0x61,R24
016C C076 RJMP 0x01E3
(0253) while(1)
(0254) {
(0255)
(0256) switch(SLSTEP)
016D 9160006D LDS R22,0x6D
016F 2777 CLR R23
0170 3164 CPI R22,0x14
0171 E0E0 LDI R30,0
0172 077E CPC R23,R30
0173 F409 BNE 0x0175
0174 C038 RJMP 0x01AD
0175 E184 LDI R24,0x14
0176 E090 LDI R25,0
0177 1786 CP R24,R22
0178 0797 CPC R25,R23
0179 F02C BLT 0x017F
017A 306A CPI R22,0xA
017B E0E0 LDI R30,0
017C 077E CPC R23,R30
017D F039 BEQ 0x0185
017E C064 RJMP 0x01E3
017F 316E CPI R22,0x1E
0180 E0E0 LDI R30,0
0181 077E CPC R23,R30
0182 F409 BNE 0x0184
0183 C04F RJMP 0x01D3
0184 C05E RJMP 0x01E3
(0257) {
(0258) case 10:
(0259)
(0260) if(SlaveEN[SlaveCR]>0)
0185 E98C LDI R24,0x9C
0186 E090 LDI R25,0
0187 91E00061 LDS R30,0x61
0189 27FF CLR R31
018A 0FE8 ADD R30,R24
018B 1FF9 ADC R31,R25
018C 8020 LDD R2,Z+0
018D 2433 CLR R3
018E 1432 CP R3,R2
018F F008 BCS 0x0191
0190 C052 RJMP 0x01E3
(0261) {
(0262)
(0263) TXbufRDY();
0191 DF50 RCALL _TXbufRDY
(0264) TXINTMAX=14;
0192 E08E LDI R24,0xE
0193 93800062 STS 0x62,R24
(0265) RXINTMAX=16;
0195 E180 LDI R24,0x10
0196 93800064 STS 0x64,R24
(0266) RXbufP=0;
0198 2422 CLR R2
0199 92200068 STS 0x68,R2
(0267) RXBUFCLR();
019B DF5E RCALL _RXBUFCLR
(0268) OUTDEON;
019C 9A94 SBI 0x12,4
(0269) TXENABLE;
019D 9854 CBI 0x0A,4
019E 9A53 SBI 0x0A,3
(0270) TXADDRESS
019F 9A50 SBI 0x0A,0
01A0 2422 CLR R2
01A1 92200060 STS 0x60,R2
(0271) TXbufP=0; //
01A3 92200067 STS 0x67,R2
(0272) //TXBUF[0]=SlaveCR;
(0273) UDR=TXBUF[0];
01A5 9020008C LDS R2,_TXBUF
01A7 B82C OUT 0x0C,R2
(0274) SLSTEP=20;
01A8 E184 LDI R24,0x14
01A9 9380006D STS 0x6D,R24
(0275) SoftTimerStart();
01AB DEA1 RCALL _SoftTimerStart
(0276) } // if(SlaveEN[SlaveCR]==1)
(0277) break;
01AC C036 RJMP 0x01E3
(0278) case 20:
(0279)
(0280) SoftTimer();
01AD DE8C RCALL _SoftTimer
(0281) if(WaitCR1>1 | (RXbufP>RXbufPmax))
01AE E081 LDI R24,1
01AF 9020006C LDS R2,0x6C
01B1 1582 CP R24,R2
01B2 F418 BCC 0x01B6
01B3 2799 CLR R25
01B4 016C MOVW R12,R24
01B5 C002 RJMP 0x01B8
01B6 24CC CLR R12
01B7 24DD CLR R13
01B8 90200069 LDS R2,0x69
01BA 90300068 LDS R3,0x68
01BC 1423 CP R2,R3
01BD F420 BCC 0x01C2
01BE E081 LDI R24,1
01BF E090 LDI R25,0
01C0 015C MOVW R10,R24
01C1 C002 RJMP 0x01C4
01C2 24AA CLR R10
01C3 24BB CLR R11
01C4 0116 MOVW R2,R12
01C5 282A OR R2,R10
01C6 283B OR R3,R11
01C7 2022 TST R2
01C8 F411 BNE 0x01CB
01C9 2033 TST R3
01CA F0C1 BEQ 0x01E3
(0282) {
(0283) RXRCK();
01CB DF3E RCALL _RXRCK
(0284) SLSTEP=30;
01CC E18E LDI R24,0x1E
01CD 9380006D STS 0x6D,R24
(0285) RXERROR=0;
01CF 2422 CLR R2
01D0 9220006A STS 0x6A,R2
(0286) }
(0287) break;
01D2 C010 RJMP 0x01E3
(0288) case 30:
(0289)
(0290) SlaveCR++;
01D3 91800061 LDS R24,0x61
01D5 5F8F SUBI R24,0xFF
01D6 93800061 STS 0x61,R24
(0291) if(SlaveCR>SlaveBMAX)
01D8 E08F LDI R24,0xF
01D9 90200061 LDS R2,0x61
01DB 1582 CP R24,R2
01DC F418 BCC 0x01E0
(0292) SlaveCR=5;
01DD E085 LDI R24,5
01DE 93800061 STS 0x61,R24
(0293) // delayXms(1);
(0294) SLSTEP=10;
FILE: <library>
01E0 E08A LDI R24,0xA
01E1 9380006D STS 0x6D,R24
01E3 CF89 RJMP 0x016D
01E4 9508 RET
pop_gset2:
01E5 E0E2 LDI R30,2
01E6 C004 RJMP pop
push_gset1:
01E7 935A ST R21,-Y
01E8 934A ST R20,-Y
01E9 9508 RET
pop_gset1:
01EA E0E1 LDI R30,1
pop:
01EB 9149 LD R20,Y+
01EC 9159 LD R21,Y+
01ED FDE0 SBRC R30,0
01EE 9508 RET
01EF 9169 LD R22,Y+
01F0 9179 LD R23,Y+
01F1 FDE1 SBRC R30,1
01F2 9508 RET
01F3 90A9 LD R10,Y+
01F4 90B9 LD R11,Y+
01F5 FDE2 SBRC R30,2
01F6 9508 RET
01F7 90C9 LD R12,Y+
01F8 90D9 LD R13,Y+
01F9 FDE3 SBRC R30,3
01FA 9508 RET
01FB 90E9 LD R14,Y+
01FC 90F9 LD R15,Y+
01FD 9508 RET
push_gset2:
01FE 937A ST R23,-Y
01FF 936A ST R22,-Y
0200 CFE6 RJMP push_gset1
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