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📄 m8mt.lst

📁 AVR MEGA8双机串行口通讯程序,单工485方式,用于单片机组网,有PROTEUS仿真电路,可以立刻验证
💻 LST
字号:
__start:
__text_start:
    001A E5CF      LDI	R28,0x5F
    001B E0D4      LDI	R29,4
    001C BFCD      OUT	0x3D,R28
    001D BFDE      OUT	0x3E,R29
    001E 51C0      SUBI	R28,0x10
    001F 40D0      SBCI	R29,0
    0020 EA0A      LDI	R16,0xAA
    0021 8308      STD	Y+0,R16
    0022 2400      CLR	R0
    0023 E6EE      LDI	R30,0x6E
    0024 E0F0      LDI	R31,0
    0025 E010      LDI	R17,0
    0026 3BEB      CPI	R30,0xBB
    0027 07F1      CPC	R31,R17
    0028 F011      BEQ	0x002B
    0029 9201      ST	R0,Z+
    002A CFFB      RJMP	0x0026
    002B 8300      STD	Z+0,R16
    002C E2E6      LDI	R30,0x26
    002D E0F0      LDI	R31,0
    002E E6A0      LDI	R26,0x60
    002F E0B0      LDI	R27,0
    0030 E010      LDI	R17,0
    0031 33E4      CPI	R30,0x34
    0032 07F1      CPC	R31,R17
    0033 F021      BEQ	0x0038
    0034 95C8      LPM
    0035 9631      ADIW	R30,1
    0036 920D      ST	R0,X+
    0037 CFF9      RJMP	0x0031
    0038 D0BA      RCALL	_main
_exit:
    0039 CFFF      RJMP	_exit
FILE: E:\m8com\M8MPt.c
(0001) //////////主机
(0002) 
(0003) #include <iom8v.h>
(0004) #include <macros.h>
(0005) //ISARM pro
(0006) #define OUTLED1OFF PORTB|=0x01       //for 
(0007) #define OUTLED1ON PORTB&=~0x01
(0008) #define OUTLED2OFF PORTB|=0x02       //For 
(0009) #define OUTLED2ON PORTB&=~0x02
(0010) #define OUTLED2Pulse PORTB^=0x02
(0011) 
(0012) #define OUTLED3OFF PORTB|=0x04      //For 
(0013) #define OUTLED3ON PORTB&=~0x04
(0014) #define OUTLED3Pulse PORTB^=0x04
(0015) #define OUTLED4OFF PORTB|=0x08      //For 
(0016) #define OUTLED4ON PORTB&=~0x08
(0017) #define OUTLED4Pulse PORTB^=0x08
(0018) 
(0019) #define OUTDEON PORTD|=0x10
(0020) #define OUTDEOFF PORTD&=~0x10
(0021) 
(0022) #define KB0 (PINC&0x01)
(0023) #define KB1 (PINC&0x02)
(0024) 
(0025) 
(0026) ///UART///
(0027) #define TXENABLE UCSRB&=~(1<<RXEN);UCSRB|=(1<<TXEN); 
(0028) #define RXENABLE UCSRB&=~(1<<TXEN);UCSRB|=(1<<RXEN); 
(0029) #define TXADDRESS UCSRB|=(1<<TXB8);TXADFG=0;
(0030) #define TXDATA UCSRB&=~(1<<TXB8);TXADFG=1;
(0031) //
(0032) #define TRFG0 0xFE
(0033) #define TRFG1 0xFD
(0034) #define TRFG2 0xF1
(0035) #define TRFG3 0xF0
(0036) //最大子板数
(0037) #define SlaveBMAX 15
(0038) //////////////////////////////
(0039) //////////////////////////////
(0040) unsigned char TXADFG=0;
(0041) 
(0042) unsigned char SlaveEN[17];
(0043) unsigned char SlaveCR=0;  //子板编号计数器,当作物理地址
(0044) unsigned char TXINTMAX=1;//下行发送中断次数控制值
(0045) //unsigned char TXINTCR=0;//下行发送中断次数计数器
(0046) unsigned char TXINTFG=0;//下行发送中断次数完成标志
(0047) unsigned char RXINTMAX=16;//下行发送中断次数控制值
(0048) unsigned char RXINTCR=0;//下行发送中断次数计数器
(0049) unsigned char RXINTFG=0;//下行发送中断次数完成标志
(0050) 
(0051) unsigned char TXBUF[30]; //发送缓冲区
(0052) unsigned char RXBUF[30];  //接收缓冲区
(0053) unsigned char TXbufP=0;  //发送缓冲区下标
(0054) unsigned char RXbufP=0;  //接收缓冲区下标
(0055) unsigned char RXbufPmax=11;//接收数据实际长度
(0056) 
(0057) unsigned char RXERROR=0;
(0058) /////Soft Timer
(0059) unsigned char WaitCR0=0;
(0060) unsigned char WaitCR1=0;
(0061) 
(0062) void SoftTimer(void)
(0063)   {
(0064)     WaitCR0++;
_SoftTimer:
    003A 9180006B  LDS	R24,0x6B
    003C 5F8F      SUBI	R24,0xFF
    003D 9380006B  STS	0x6B,R24
(0065) 	if(WaitCR0>254)
    003F EF8E      LDI	R24,0xFE
    0040 9020006B  LDS	R2,0x6B
    0042 1582      CP	R24,R2
    0043 F440      BCC	0x004C
(0066) 	 {
(0067) 	  WaitCR0=0;
    0044 2422      CLR	R2
    0045 9220006B  STS	0x6B,R2
(0068) 	  WaitCR1++;
    0047 9180006C  LDS	R24,0x6C
    0049 5F8F      SUBI	R24,0xFF
    004A 9380006C  STS	0x6C,R24
(0069) 	 }//if(WaitCR0>0)
    004C 9508      RET
(0070)   }
(0071) void SoftTimerStart(void)
(0072)   {
(0073)    WaitCR0=0;
_SoftTimerStart:
    004D 2422      CLR	R2
    004E 9220006B  STS	0x6B,R2
(0074)    WaitCR1=0;
    0050 9220006C  STS	0x6C,R2
    0052 9508      RET
(0075)   }
(0076)   
(0077) void watchdog_init(void)
(0078)      {
(0079) 	   WDR();
_watchdog_init:
    0053 95A8      WDR
(0080) 	   WDTCR=0x0F ;
    0054 E08F      LDI	R24,0xF
    0055 BD81      OUT	0x21,R24
    0056 9508      RET
(0081) 	 }
(0082) 	 
(0083) void Delay_1ms(void)
(0084) 	{
(0085) 	unsigned int i;
(0086) 
(0087) 	for (i = 1; i<1140; i++)
_Delay_1ms:
  i                    --> R16
    0057 E001      LDI	R16,1
    0058 E010      LDI	R17,0
    0059 C002      RJMP	0x005C
    005A 5F0F      SUBI	R16,0xFF
    005B 4F1F      SBCI	R17,0xFF
    005C 3704      CPI	R16,0x74
    005D E0E4      LDI	R30,4
    005E 071E      CPC	R17,R30
    005F F3D0      BCS	0x005A
    0060 9508      RET
_delayXms:
  i                    --> R20
  n                    --> R22
    0061 D0C2      RCALL	push_gset2
    0062 01B8      MOVW	R22,R16
(0088) 		
(0089) 			;
(0090) 	}
(0091) 
(0092) void delayXms(unsigned int n)
(0093)      {
(0094) 	   unsigned int i=0;
    0063 2744      CLR	R20
    0064 2755      CLR	R21
    0065 C003      RJMP	0x0069
(0095) 	   while(i<n)
(0096) 	     {
(0097) 		  Delay_1ms();
    0066 DFF0      RCALL	_Delay_1ms
(0098) 		  i++;
    0067 5F4F      SUBI	R20,0xFF
    0068 4F5F      SBCI	R21,0xFF
    0069 1746      CP	R20,R22
    006A 0757      CPC	R21,R23
    006B F3D0      BCS	0x0066
    006C D09E      RCALL	pop_gset2
    006D 9508      RET
(0099) 		 }
(0100) 	 }
(0101) 	 
(0102) 	 
(0103) void port_init(void)
(0104)      {
(0105) 	 
(0106) 					 
(0107) 	  PORTB=0xFF;    //PB set to 1
_port_init:
    006E EF8F      LDI	R24,0xFF
    006F BB88      OUT	0x18,R24
(0108) 	  DDRB=0xFF;     
    0070 BB87      OUT	0x17,R24
(0109) 					 
(0110) 	  PORTC=0xFF;    //PC set to 1
    0071 BB85      OUT	0x15,R24
(0111) 	  DDRC=0x00;     //
    0072 2422      CLR	R2
    0073 BA24      OUT	0x14,R2
(0112) 	      
(0113) 	  PORTD=0xFF;    //PD set to 1
    0074 BB82      OUT	0x12,R24
(0114) 	  DDRD=0x12;     //PD0:RXD PD1:TXD PD2:DI0 PD3:DI1
    0075 E182      LDI	R24,0x12
    0076 BB81      OUT	0x11,R24
(0115) 	                 //PD4:DI2  PD5:DI3 
(0116) 	  //OUTDEON;
(0117) 	  
(0118) 	SFIOR&=~(1<<PUD);  //OPEN UP LINK
    0077 B780      IN	R24,0x30
    0078 7F8B      ANDI	R24,0xFB
    0079 BF80      OUT	0x30,R24
(0119) 	//MCUCR|=(1<<ISC11); //Down edge int1
(0120) 	//GICR=(1<<INT1); //enable INT1
(0121) 	  
(0122) 	  delayXms(10); //delay 1s
    007A E00A      LDI	R16,0xA
    007B E010      LDI	R17,0
    007C DFE4      RCALL	_delayXms
    007D 9508      RET
(0123) 	 }
(0124) //////////////////////////UART INIT
(0125) void uart_init(void) 
(0126)    {
(0127)     
(0128)     OUTDEOFF;
_uart_init:
    007E 9894      CBI	0x12,4
(0129)     UCSRB=0x00;
    007F 2422      CLR	R2
    0080 B82A      OUT	0x0A,R2
(0130) 	UBRRL=0x25;  //19.2kbps
    0081 E285      LDI	R24,0x25
    0082 B989      OUT	0x09,R24
(0131) 	//TX EN ,9Bit ,Adress init
(0132) 	UCSRB=((1<<RXCIE)|(1<<TXCIE)|(1<<UCSZ2));
    0083 EC84      LDI	R24,0xC4
    0084 B98A      OUT	0x0A,R24
    0085 9508      RET
(0133) 	//UCSRB=((1<<TXCIE)|(1<<TXCIE)|(1<<TXEN)|(1<<TXB8));
(0134)    }//void uart_init(void) 
(0135) 
(0136) ///////////////Timer init	 
(0137) void timer_init(void)
(0138)      {
(0139) 	  ;
_timer_init:
    0086 9508      RET
(0140) 	 }	 	 
(0141) 	
(0142) 
(0143) #pragma interrupt_handler timer1_ovf_isr:9
(0144) void timer1_ovf_isr(void)
(0145) {	
(0146) 	 ;  
_timer1_ovf_isr:
    0087 9518      RETI
_uart1_tx_isr:
    0088 922A      ST	R2,-Y
    0089 938A      ST	R24,-Y
    008A 939A      ST	R25,-Y
    008B 93EA      ST	R30,-Y
    008C 93FA      ST	R31,-Y
    008D B62F      IN	R2,0x3F
    008E 922A      ST	R2,-Y
(0147) 	 
(0148) }//void timer1_ovf_isr(void)
(0149) 
(0150) //TR to SLAVE
(0151) #pragma interrupt_handler uart1_tx_isr:14
(0152) void uart1_tx_isr(void)
(0153)  {  
(0154)     TXbufP++;
    008F 91800067  LDS	R24,0x67
    0091 5F8F      SUBI	R24,0xFF
    0092 93800067  STS	0x67,R24
(0155) 	
(0156) 	  
(0157) 	if(TXbufP<14)
    0094 308E      CPI	R24,0xE
    0095 F4A0      BCC	0x00AA
(0158) 	  {
(0159)        
(0160) 	   if(TXbufP==2 )
    0096 3082      CPI	R24,2
    0097 F441      BNE	0x00A0
(0161) 	     {
(0162) 	     OUTLED3Pulse;
    0098 E084      LDI	R24,4
    0099 B228      IN	R2,0x18
    009A 2628      EOR	R2,R24
    009B BA28      OUT	0x18,R2
(0163) 	    // Delay_1ms();
(0164) 	     //delayXms(1000);
(0165) 		 TXDATA;
    009C 9850      CBI	0x0A,0
    009D E081      LDI	R24,1
    009E 93800060  STS	0x60,R24
(0166) 		 
(0167) 		 //OUTLED3Pulse;
(0168) 	     //
(0169) 	     }//if(TXbufP>1)
(0170) 		UDR=TXBUF[TXbufP]; 
    00A0 E88C      LDI	R24,0x8C
    00A1 E090      LDI	R25,0
    00A2 91E00067  LDS	R30,0x67
    00A4 27FF      CLR	R31
    00A5 0FE8      ADD	R30,R24
    00A6 1FF9      ADC	R31,R25
    00A7 8020      LDD	R2,Z+0
    00A8 B82C      OUT	0x0C,R2
(0171) 	  }
    00A9 C003      RJMP	0x00AD
(0172) 	else
(0173) 	    {
(0174) 		 OUTLED1ON;
    00AA 98C0      CBI	0x18,0
(0175) 		 RXENABLE
    00AB 9853      CBI	0x0A,3
    00AC 9A54      SBI	0x0A,4
(0176) 		}//else
(0177) 	OUTLED2Pulse;
    00AD E082      LDI	R24,2
    00AE B228      IN	R2,0x18
    00AF 2628      EOR	R2,R24
    00B0 BA28      OUT	0x18,R2
    00B1 9029      LD	R2,Y+
    00B2 BE2F      OUT	0x3F,R2
    00B3 91F9      LD	R31,Y+
    00B4 91E9      LD	R30,Y+
    00B5 9199      LD	R25,Y+
    00B6 9189      LD	R24,Y+
    00B7 9029      LD	R2,Y+
    00B8 9518      RETI
_uart1_rx_isr:
    00B9 922A      ST	R2,-Y
    00BA 938A      ST	R24,-Y
    00BB 939A      ST	R25,-Y
    00BC 93EA      ST	R30,-Y
    00BD 93FA      ST	R31,-Y
    00BE B62F      IN	R2,0x3F
    00BF 922A      ST	R2,-Y
(0178) 	//Delay_1ms();
(0179) 	//OUTLED2Pulse;
(0180)  }//void uart1_tx_isr(void)
(0181) 
(0182) #pragma interrupt_handler uart1_rx_isr:12
(0183) void uart1_rx_isr(void)
(0184)  {	
(0185)     RXBUF[RXbufP]=UDR;
    00C0 E68E      LDI	R24,0x6E
    00C1 E090      LDI	R25,0
    00C2 91E00068  LDS	R30,0x68
    00C4 27FF      CLR	R31
    00C5 0FE8      ADD	R30,R24
    00C6 1FF9      ADC	R31,R25
    00C7 B02C      IN	R2,0x0C
    00C8 8220      STD	Z+0,R2
(0186) 	RXbufP++;
    00C9 91800068  LDS	R24,0x68
    00CB 5F8F      SUBI	R24,0xFF
    00CC 93800068  STS	0x68,R24
(0187) 	if(RXBUF[11]==TRFG3)
    00CE 91800079  LDS	R24,0x79
    00D0 3F80      CPI	R24,0xF0
    00D1 F409      BNE	0x00D3
(0188) 	   OUTLED4ON;
    00D2 98C3      CBI	0x18,3
    00D3 9029      LD	R2,Y+
    00D4 BE2F      OUT	0x3F,R2
    00D5 91F9      LD	R31,Y+
    00D6 91E9      LD	R30,Y+
    00D7 9199      LD	R25,Y+
    00D8 9189      LD	R24,Y+
    00D9 9029      LD	R2,Y+
    00DA 9518      RETI
(0189) 	
(0190)  }//void uart1_rx_isr(void)
(0191) void TXbufRDY(void)
(0192) {
(0193)  TXBUF[0]=5;
_TXbufRDY:
    00DB E085      LDI	R24,5
    00DC 9380008C  STS	_TXBUF,R24
(0194)  TXBUF[1]=5;
    00DE 9380008D  STS	_TXBUF+1,R24
(0195)  TXBUF[2]=TRFG0;
    00E0 EF8E      LDI	R24,0xFE
    00E1 9380008E  STS	_TXBUF+2,R24
(0196)  TXBUF[3]=TRFG1;
    00E3 EF8D      LDI	R24,0xFD
    00E4 9380008F  STS	_TXBUF+3,R24
(0197)  TXBUF[4]=0;
    00E6 2422      CLR	R2
    00E7 92200090  STS	0x90,R2
(0198)  TXBUF[5]=1;
    00E9 E081      LDI	R24,1
    00EA 93800091  STS	0x91,R24
(0199)  TXBUF[12]=TRFG2;
    00EC EF81      LDI	R24,0xF1
    00ED 93800098  STS	0x98,R24
(0200)  TXBUF[13]=TRFG3;
    00EF EF80      LDI	R24,0xF0
    00F0 93800099  STS	0x99,R24
    00F2 9508      RET
(0201) }//void TXbufRDY(void)
(0202) 
(0203) 
(0204) 
(0205) unsigned char SLSTEP=10;
(0206) void main()
(0207) {
(0208)    unsigned char i=0;
_main:
  i                    --> R20
    00F3 2744      CLR	R20
(0209)    
(0210) 	//delayXms(500); 
(0211) 	port_init(); //IO初始化	
    00F4 DF79      RCALL	_port_init
(0212) 	uart_init();
    00F5 DF88      RCALL	_uart_init
(0213) 	//timer_init();
(0214) 	
(0215) 	delayXms(100); 
    00F6 E604      LDI	R16,0x64
    00F7 E010      LDI	R17,0
    00F8 DF68      RCALL	_delayXms
(0216) 	RXbufP=0;
    00F9 2422      CLR	R2
    00FA 92200068  STS	0x68,R2
(0217) 	TXbufRDY()
    00FC DFDE      RCALL	_TXbufRDY
    00FD 9478      BSET	7
(0218) 	SEI();
(0219) 	TXbufP=0;
    00FE 2422      CLR	R2
    00FF 92200067  STS	0x67,R2
(0220) 	TXADDRESS;
    0101 9A50      SBI	0x0A,0
    0102 92200060  STS	0x60,R2
(0221) 	TXENABLE;
    0104 9854      CBI	0x0A,4
    0105 9A53      SBI	0x0A,3
(0222) 	UDR=TXBUF[0];
    0106 9020008C  LDS	R2,_TXBUF
    0108 B82C      OUT	0x0C,R2
(0223) 	while(1)
FILE: <library>
    0109 CFFF      RJMP	0x0109
    010A 9508      RET
pop_gset2:
    010B E0E2      LDI	R30,2
    010C C004      RJMP	pop
push_gset1:
    010D 935A      ST	R21,-Y
    010E 934A      ST	R20,-Y
    010F 9508      RET
pop_gset1:
    0110 E0E1      LDI	R30,1
pop:
    0111 9149      LD	R20,Y+
    0112 9159      LD	R21,Y+
    0113 FDE0      SBRC	R30,0
    0114 9508      RET
    0115 9169      LD	R22,Y+
    0116 9179      LD	R23,Y+
    0117 FDE1      SBRC	R30,1
    0118 9508      RET
    0119 90A9      LD	R10,Y+
    011A 90B9      LD	R11,Y+
    011B FDE2      SBRC	R30,2
    011C 9508      RET
    011D 90C9      LD	R12,Y+
    011E 90D9      LD	R13,Y+
    011F FDE3      SBRC	R30,3
    0120 9508      RET
    0121 90E9      LD	R14,Y+
    0122 90F9      LD	R15,Y+
    0123 9508      RET
push_gset2:
    0124 937A      ST	R23,-Y
    0125 936A      ST	R22,-Y
    0126 CFE6      RJMP	push_gset1

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