stv0299.c

STV0299 driver,DVB_S QPSK channel demodule

#include "Main.h"
#include <tsk.h>
/* Master Clock = 88 MHz */
#include "stv0299.h"

#define M_CLK (88000000UL) 

#define check_max_num    10000

#define Int int
#define UInt unsigned int

static	UInt32		m_glTunerType = 0;
static struct qpsk_frontend_parameters dvb_dfp;
extern SaveAllConfig g_tSaveAllConfig;
extern I2C_Config IIC_ConfigR;
extern REG0299Info g_tREG0299Info;
extern int g_nRFLockStatus;
extern int g_nRFLock;
extern int g_nUnlockTimeout;

Int iicwriteregs(UInt8 sl_add,UInt8 sub_add,UInt8* data,int num);
Int iicReadregs(UInt8 sl_add, UInt8 sub_add, UInt8* data,int num);
int stb6000_IIC_read(I2C_Handle hI2C,
              Uint8 devAddress,
              Uint32  subAddress,
              Uint8 *data,
              Uint16  numBytes
              );

struct dvb_frontend_info  fe_stv0299_info = {
     "STV0299 based",
	 FE_QPSK,
     950000,
	 2150000,
	 125,   /* kHz for QPSK frontends */  
	 M_CLK/2000,
	 1000000,
	 45000000,
	 500,  /* ppm */
     0,
	 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
	      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
	      FE_CAN_QPSK |
	      FE_CAN_FEC_AUTO | FE_CAN_INVERSION_AUTO 
	     
};

UInt8  init_tab1 [] = {
        /* clock registers */
    0x01, 0x15,   /* K = 0, DIRCLK = 0, M = 0x15                  */
	0x02, 0x30,   /* STDBY = 0, VCO = 0 (ON), SERCLK = 0, P = 0   */
                      /* f_VCO = 4MHz * 4 * (M+1) / (K+1) = 352 MHz   */
	0x03, 0x00,   /* auxiliary clock not used                     */
	0x04, 0x7d,   /* F22FR = 0x7d                                 */
		      /* F22 = f_VCO / 128 / 0x7d = 22 kHz            */

        /* I2C bus repeater */
	0x05, 0x35,   /* I2CT = 0, SCLT = 1, SDAT = 1                 */

 	/* general purpose DAC registers */
	0x06, 0x40,   /* DAC not used, set to high impendance mode    */
	0x07, 0x00,   /* DAC LSB                                      */

	/* DiSEqC registers */
	0x08, 0x40,   /* DiSEqC off                                   */
	0x09, 0x00,   /* FIFO                                         */

        /* Input/Output configuration register */
	0x0c, 0x51,   /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
	              /* OP0 ctl = Normal, OP0 val = 1 (18 V)         */
                      /* Nyquist filter = 00, QPSK reverse = 0        */
                   
        /* AGC1 control register */
	0x0d, 0x82,   /* DC offset compensation = ON, beta_agc1 = 2   */

        /* Timing loop register */
	0x0e, 0x23,   /* alpha_tmg = 2, beta_tmg = 3                  */
    0x0f, 0xd4,   /* Iagc = Normal,  m1 = 18 */

	0x10, 0x34,   // AGC2  0x3d
	0x11, 0x84,
	0x12, 0xb7,   // Lock detect: -64  Carrier freq detect:on
	0x13, 0xb6,   // alpha_car b:4 a:0  noise est:256ks  derot:on
	0x14, 0x93,   // beat carc:0 d:0 e:0xf  phase detect algo: 1
	0x15, 0xc9,   // lock detector threshold

	0x16, 0x1d,   /* AGC1 integrator value                        */
	0x17, 0x00,
	0x18, 0x14,
	0x19, 0xf2,

	0x1a, 0x11,

	0x1b, 0x9c,
	0x1c, 0x00,
	0x1d, 0x00,
	0x1e, 0x0b,
	0x1f, 0x50,

	0x20, 0x00,
	0x21, 0x00,
	0x22, 0x00,
	0x23, 0x00,
	0x24, 0xff,
	0x25, 0xff,
	0x26, 0xff,

	0x28, 0x00,  // out imp: normal  out type: parallel FEC mode:0
	0x29, 0x1e,  // 1/2 threshold
	0x2a, 0x14,  // 2/3 threshold
	0x2b, 0x0f,  // 3/4 threshold
	0x2c, 0x09,  // 5/6 threshold
	0x2d, 0x05,  // 7/8 threshold
	0x2e, 0x01,

	0x31, 0x1f,  // test all FECs

	0x32, 0x19,  // viterbi and synchro search
	0x33, 0xfc,  // rs control
	0x34, 0x13,  //0x93,  // error control

	0x0b, 0x00,
	0x27, 0x00,
	0x2f, 0x00,
	0x30, 0x00,
	0x35, 0x00,
	0x36, 0x00,
	0x37, 0x00,
	0x38, 0x00,
	0x39, 0x00,
	0x3a, 0x00,
	0x3b, 0x00,
	0x3c, 0x00,
	0x3d, 0x00,
	0x3e, 0x00,
	0x3f, 0x00,
	0x40, 0x00,
	0x41, 0x00,
	0x42, 0x00,
	0x43, 0x00,
	0x44, 0x00,
	0x45, 0x00,
	0x46, 0x00,
	0x47, 0x00,
	0x48, 0x00,
	0x49, 0x00,
	0x4a, 0x00,
	0x4b, 0x00,
	0x4c, 0x00,
	0x4d, 0x00,
	0x4e, 0x00,
	0x4f, 0x00
};

UInt8  init_value[] = {
        /* clock registers */
    /*0x01,*/ 0x15,   /* K = 0, DIRCLK = 0, M = 0x15                  */
	/*0x02,*/ 0x30,   /* STDBY = 0, VCO = 0 (ON), SERCLK = 0, P = 0   */
                      /* f_VCO = 4MHz * 4 * (M+1) / (K+1) = 352 MHz   */
	/*0x03,*/ 0x00,   /* auxiliary clock not used                     */
	/*0x04,*/ 0x7d,   /* F22FR = 0x7d                                 */
		      /* F22 = f_VCO / 128 / 0x7d = 22 kHz            */

        /* I2C bus repeater */
	/*0x05,*/ 0x35,   /* I2CT = 0, SCLT = 1, SDAT = 1                 */

 	/* general purpose DAC registers */
	/*0x06,*/ 0x40,   /* DAC not used, set to high impendance mode    */
	/*0x07,*/ 0x00,   /* DAC LSB                                      */

	/* DiSEqC registers */
	/*0x08,*/ 0x40,   /* DiSEqC off                                   */
	/*0x09, */0x00,   /* FIFO 	*/
	/*0x0a, */0x00, 
	/*0x0b, */0x00,
        /* Input/Output configuration register */
	/*0x0c,*/ 0x51,   /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
	              /* OP0 ctl = Normal, OP0 val = 1 (18 V)         */
                      /* Nyquist filter = 00, QPSK reverse = 0        */
                   
        /* AGC1 control register */
	/*0x0d,*/ 0x82,   /* DC offset compensation = ON, beta_agc1 = 2   */

        /* Timing loop register */
	/*0x0e,*/ 0x23,   /* alpha_tmg = 2, beta_tmg = 3                  */
    /*0x0f,*/ 0xd4,   /* Iagc = Normal,  m1 = 18 */

	/*0x10,*/ 0x34,   // AGC2  0x3d
	/*0x11,*/ 0x84,
	/*0x12,*/ 0xb7,   // Lock detect: -64  Carrier freq detect:on
	/*0x13,*/ 0xb6,   // alpha_car b:4 a:0  noise est:256ks  derot:on
	/*0x14,*/ 0x93,   // beat carc:0 d:0 e:0xf  phase detect algo: 1
	/*0x15,*/ 0xc9,   // lock detector threshold

	/*0x16,*/ 0x1d,   /* AGC1 integrator value                        */
	/*0x17,*/ 0x00,
	/*0x18,*/ 0x14,
	/*0x19,*/ 0xf2,

	/*0x1a,*/ 0x11,

	/*0x1b,*/ 0x9c,
	/*0x1c,*/ 0x00,
	/*0x1d,*/ 0x00,
	/*0x1e,*/ 0x0b,
	/*0x1f,*/ 0x50,

	/*0x20,*/ 0x00,
	/*0x21,*/ 0x00,
	/*0x22,*/ 0x00,
	/*0x23,*/ 0x00,
	/*0x24,*/ 0xff,
	/*0x25,*/ 0xff,
	/*0x26,*/ 0xff,
	/*0x27,*/ 0x00,
	/*0x28,*/ 0x00,  // out imp: normal  out type: parallel FEC mode:0
	/*0x29,*/ 0x1e,  // 1/2 threshold
	/*0x2a,*/ 0x14,  // 2/3 threshold
	/*0x2b,*/ 0x0f,  // 3/4 threshold
	/*0x2c,*/ 0x09,  // 5/6 threshold
	/*0x2d,*/ 0x05,  // 7/8 threshold
	/*0x2e,*/ 0x01,
	/*0x2f,*/ 0x00,
	/*0x30,*/ 0x00,
	/*0x31,*/ 0x1f,  // test all FECs

	/*0x32,*/ 0x19,  // viterbi and synchro search
	/*0x33,*/ 0xfc,  // rs control
	/*0x34,*/ 0x13,  //0x93,  // error control

	/*0x35,*/ 0x00,
	/*0x36,*/ 0x00,
	/*0x37,*/ 0x00,
	/*0x38,*/ 0x00,
	/*0x39,*/ 0x00,
	/*0x3a,*/ 0x00,
	/*0x3b,*/ 0x00,
	/*0x3c,*/ 0x00,
	/*0x3d,*/ 0x00,
	/*0x3e,*/ 0x00,
	/*0x3f,*/ 0x00,
	
	/*0x40,*/ 0x00,
	/*0x41,*/ 0x00,
	/*0x42,*/ 0x00,
	/*0x43,*/ 0x00,
	/*0x44,*/ 0x00,
	/*0x45,*/ 0x00,
	/*0x46,*/ 0x00,
	/*0x47,*/ 0x00,
	
	/*0x48,*/ 0x00,
	/*0x49,*/ 0x00,
	/*0x4a,*/ 0x00,
	/*0x4b,*/ 0x00,
	/*0x4c,*/ 0x00,
	/*0x4d,*/ 0x00,
	/*0x4e,*/ 0x00,
};


void  delay(UInt32 num)
{
	UInt32 i,j;
	for(i=0;i<num;i++)
	{
		j=1024*5000;
		while (j==0) {
			j--;
		}
	}
}

Int iicwriteregs(UInt8 sl_add,UInt8 sub_add,UInt8* data,int num)
{
	_IIC_write(EVMDM642_I2C_hI2C, sl_add, sub_add, data, num);
	return 0;
}


Int iicReadregs(UInt8 sl_add, UInt8 sub_add, UInt8* data,int num)
{
	_IIC_read(EVMDM642_I2C_hI2C, sl_add, sub_add, data, num);
	return 0;
}


void QPSK_tuner_init()
{
	stv0299_init ();
	dvb_dfp.frequency   = g_tSaveAllConfig.tAllConfig.DeModuleInfo.frequency;
	dvb_dfp.fec_inner   = FEC_AUTO;
	dvb_dfp.inversion   = INVERSION_AUTO;
	dvb_dfp.symbol_rate = g_tSaveAllConfig.tAllConfig.DeModuleInfo.SymbolRate;
	
	stv0299_set_frontend(&dvb_dfp);
//	stv0299_get_frontend(&dvb_dfp);
	stv0299_check_status();
}

int stv0299_writereg (UInt8 reg, UInt8 data)
{
	MULT_IIC_WRITE(EVMDM642_I2C_hI2C, stv0299_adw, reg, &data, 1);
	return 0;
}


int stv0299_writeregs (UInt8 reg, UInt8 *data, int len)
{
    MULT_IIC_WRITE(EVMDM642_I2C_hI2C, stv0299_adw, reg, data, len);
	return 0;
}


UInt8  stv0299_readreg (UInt8 reg )
{
	UInt8 data;
	MULT_IIC_READ(EVMDM642_I2C_hI2C, stv0299_adr, reg, &data, 1);
	return data;
}



int stv0299_readregs ( UInt8 reg1, UInt8 *b, UInt8 len)
{
    int ret;
	int i;
	Uint8 temp;

    ret=0;		
	for(i=0;i<len;i++)
	{
//		ret=iicReadReg(stv0299_adr,reg1, &temp);
               
		MULT_IIC_READ(EVMDM642_I2C_hI2C, stv0299_adr, reg1, &temp, 1);

		 reg1++;
		 b[i]=(UInt8)temp;
		 
	}
     
    return ret;
}


int stb6000_set_tv_freq	(struct qpsk_frontend_parameters *p)
{  
	
	UInt8 table[]={0x00,0xba,0x3b,0x60,0x04,0x07,0x8f,0xd8,0xd0,0x50,0xeb,0x4f};
	UInt8 table1[]={0x00,0x79,0x3b,0x60,0x04,0x07,0x8f,0xdf,0xd0,0x50,0xfb,0x4f};
//	Uint8 tableTmp[16];
	UInt8 osm;
	UInt16 freqm,n,a,f,t;
	UInt32 freq,vco;

//	UInt8 regs[13];
	UInt8 table2[]={0x00,0x00,0x58,0x00,0x62,0x0a};
	freq=p->frequency;
	if (freq<950000) 	   freq=950000;
	if (freq>2150000) 	   freq=2150000;
	
	if(m_glTunerType != 0x08)
	{
		if (freq>949000)   osm=0xba;
		if (freq>999000)   osm=0xbc;
		if (freq>1075000)  osm=0xa0;
		if (freq>1199000)  osm=0xa1;
		if (freq>1299000)  osm=0xa2;
		if (freq>1369000)  osm=0xa4;
		if (freq>1469000)  osm=0xa5;
		if (freq>1529000)  osm=0xa6;
		if (freq>1649000)  osm=0xa8;
		if (freq>1799000)  osm=0xaa;
		if (freq>1949000)  osm=0xac;
		
		table[1]=osm;
		f=(p->symbol_rate+500000)/1000000; 
		if (f>30) {
			f=30;
		}
		table[6]=f&0x1f;
		
		freqm = (UInt16)(freq /1000);
		if (freqm<1075) {
			n=freqm >>3;
			a=(freqm<<1) & 0x000f;
		}
		else{
			n=freqm >>4;
			a=freqm & 0x000f;
		}
		table[2]=(n>>1) & 0xff;
		table[3] |=(n << 7) | (a & 0x0f);
		
		
		stv0299_writereg( 0x05, 0xb5);   	/*  enable i2c repeater on stv0299  */
		iicwriteregs( stb6000_adw, 1,&table[1],11);
//		stv0299_writereg( 0x05, 0xb5);   	/*  enable i2c repeater on stv0299  */
//		stb6000_IIC_read(EVMDM642_I2C_hI2C, stb6000_adr,0,tableTmp,12);
//		stv0299_writereg(0x05, 0x35);   	/*  disable i2c repeater on stv0299  */ 
		
		stv0299_writereg( 0x05, 0xb5);   	/*  enable i2c repeater on stv0299  */
		iicwriteregs( stb6000_adw, 7,&table1[7],4);
//		stv0299_writereg(0x05, 0x35);   	/*  disable i2c repeater on stv0299  */ 
	}
	else
	{
		vco=freq*2;
		if (freq<1125000)  
		{
			table2[0] =0x00;
			vco=freq*4;		 
		}
		else
		{
			
			table2[0] =0x80;
		}
		osm=0;
		if (vco>2432000)   osm=0x01;
		if (vco>2710000)   osm=0x02;
		if (vco>3024000)  osm=0x03;
		if (vco>3340000)  osm=0x04;
		if (vco>3726000)  osm=0x05;
		if (vco>4142000)  osm=0x06;
		if (vco>4492000)  osm=0x07;
		table2[2]|=osm;
		
		f=(p->symbol_rate/2-4000000)/1000000; 
		
		t=(f*1000+144)/145;
		table2[3]=t&0x007f;
		freqm=(UInt16)(freq /500);
		table2[1]=freqm & 0x00ff;
		table2[0]|=(freqm>>8) & 0x007f;
		stv0299_writereg( 0x05, 0xb5);   	/*  enable i2c repeater on stv0299  */
		iicwriteregs((0xc0>>1),0,&table2[0],6);
		stv0299_writereg(0x05, 0x35);   	/*  disable i2c repeater on stv0299  */ 
		
	}
	
    return 0;
}



int stv0299_init ()
{
	stv0299_writeregs( 1, init_value, 0x4e);
//	for(i=1; i<0x4f; i++)
//				data = stv0299_readreg(i);
//	data = stv0299_readreg(0x1b);
// 	if(m_glTunerType == 0x08) { stv0299_writereg (0x0f, 0x54); } /* Iagc = Normal,  m1 = 18 */
//	else { stv0299_writereg (0x0f, 0xd4);  }

	return 0;
}


int stv0299_check_inversion ()
{
	UInt8 val;  
	val = stv0299_readreg (0x0c);
	stv0299_writereg ( 0x0c, val ^ 0x01);


	stv0299_writereg ( 0x22, 0x00);
	stv0299_writereg ( 0x23, 0x00);
	stv0299_readreg ( 0x23);
	stv0299_writereg ( 0x12, 0xb9); //0xb9
	
	return 0;
}



int stv0299_set_FEC ( fe_code_rate_t fec)
{
   

	switch (fec) {
	case FEC_AUTO:
		return stv0299_writereg ( 0x31, 0x1f);
	case FEC_1_2:
		return stv0299_writereg ( 0x31, 0x01);
	case FEC_2_3:
		return stv0299_writereg ( 0x31, 0x02);
	case FEC_3_4:
		return stv0299_writereg ( 0x31, 0x04);
	case FEC_5_6:
		return stv0299_writereg ( 0x31, 0x08);
	case FEC_7_8:
		return stv0299_writereg ( 0x31, 0x10);
	default:
		return -EINVAL;
	}
}



fe_code_rate_t stv0299_get_fec ()
{
	 fe_code_rate_t fec_tab [] = { FEC_2_3, FEC_3_4, FEC_5_6,
					     FEC_7_8, FEC_1_2 };
	UInt8 index;

 

	index = stv0299_readreg (0x1b);
	index &= 0x7;

	if (index > 4)
		return FEC_AUTO;

	return fec_tab [index];
}




int stv0299_wait_diseqc_fifo ( int timeout)
{
      int  start = 0;

	while (stv0299_readreg(0x0a) & 1) {
		if ( start > timeout) {
			
			return 1;
		}
	 start++;
    // add delay her   

		};

	return 0;
}



int stv0299_wait_diseqc_idle ( int timeout)
{
    int  start = 0;

	while ((stv0299_readreg(0x0a) & 3) != 2 ) {
		if (start > timeout) {
		return 1;
		}
     start++;
	 //add delay here

	};

	return 0;
}



int stv0299_send_diseqc_msg ( struct dvb_diseqc_master_cmd *m)
{
	UInt8 val;
	int i;

	 
	if (stv0299_wait_diseqc_idle ( 100) )
		return 1;

	val = stv0299_readreg (0x08);

	if (stv0299_writereg (0x08, (val & ~0x7) | 0x6))  /* DiSEqC mode */