lab5.map.rpt

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; LPM_WIDTHR                                     ; 8        ; Untyped             ;
; LPM_WIDTHS                                     ; 1        ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped             ;
; LPM_PIPELINE                                   ; 0        ; Untyped             ;
; LATENCY                                        ; 0        ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped             ;
; USE_EAB                                        ; OFF      ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped             ;
; DEVICE_FAMILY                                  ; Stratix  ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped             ;
+------------------------------------------------+----------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                      ;
+---------------------------------------+-----------------------------+
; Name                                  ; Value                       ;
+---------------------------------------+-----------------------------+
; Number of entity instances            ; 1                           ;
; Entity Instance                       ; cpu:cpu|lpm_mult:mult_rtl_0 ;
;     -- LPM_WIDTHA                     ; 4                           ;
;     -- LPM_WIDTHB                     ; 4                           ;
;     -- LPM_WIDTHP                     ; 8                           ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                    ;
;     -- INPUT_A_IS_CONSTANT            ; NO                          ;
;     -- INPUT_B_IS_CONSTANT            ; NO                          ;
;     -- USE_EAB                        ; OFF                         ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                        ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                          ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                          ;
+---------------------------------------+-----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/lab5/lab5.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Oct 10 01:18:47 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab5 -c lab5
Info: Found 1 design units, including 1 entities, in source file cpu.v
    Info: Found entity 1: cpu
Info: Found 1 design units, including 1 entities, in source file lab2_sim.v
    Info: Found entity 1: lab2_sim
Info: Found 1 design units, including 1 entities, in source file memory.v
    Info: Found entity 1: memory
Info: Found 1 design units, including 1 entities, in source file prog_ram.v
    Info: Found entity 1: prog_ram
Info: Elaborating entity "lab2_sim" for the top level hierarchy
Info: Elaborating entity "cpu" for hierarchy "cpu:cpu"
Warning: Verilog HDL assignment warning at cpu.v(26): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(32): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(35): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(39): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(43): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(47): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(51): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(55): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(59): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(74): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(90): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at cpu.v(98): truncated value with size 32 to match size of target (5)
Warning: (10270) Verilog HDL statement warning at cpu.v(31): incomplete Case Statement has no default case item
Info: Elaborating entity "memory" for hierarchy "memory:memory"
Warning: (10270) Verilog HDL statement warning at memory.v(19): incomplete Case Statement has no default case item
Warning: (10270) Verilog HDL statement warning at memory.v(27): incomplete Case Statement has no default case item
Info: Elaborating entity "prog_ram" for hierarchy "prog_ram:prog_ram"
Warning: (10270) Verilog HDL statement warning at prog_ram.v(7): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at prog_ram.v(6): variable "instruction" may not be assigned a new value in every possible path through the Always Construct.  Variable "instruction" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Reduced register "cpu:cpu|mem_read_addr[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "cpu:cpu|mem_write_addr[3]" with stuck data_in port to stuck value GND
Info: State machine "|lab2_sim|cpu:cpu|flag" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|lab2_sim|cpu:cpu|flag"
Info: Encoding result for state machine "|lab2_sim|cpu:cpu|flag"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "cpu:cpu|flag.00"
        Info: Encoded state bit "cpu:cpu|flag.10"
        Info: Encoded state bit "cpu:cpu|flag.01"
    Info: State "|lab2_sim|cpu:cpu|flag.00" uses code string "000"
    Info: State "|lab2_sim|cpu:cpu|flag.01" uses code string "101"
    Info: State "|lab2_sim|cpu:cpu|flag.10" uses code string "110"
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/multcore.tdf
    Info: Found entity 1: multcore
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/mpar_add.tdf
    Info: Found entity 1: mpar_add
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../quartus50sp1/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Latch prog_ram:prog_ram|instruction[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Latch prog_ram:prog_ram|instruction[11] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal cpu:cpu|ram_addr[4]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "instruction[3]" stuck at GND
    Warning: Pin "instruction[6]" stuck at GND
    Warning: Pin "instruction[7]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 241 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 28 output pins
    Info: Implemented 211 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings
    Info: Processing ended: Wed Oct 10 01:18:55 2007
    Info: Elapsed time: 00:00:10