lab5.map.eqn

若若無法引言人元mpeg2 decode

C1_b[2]_lut_out = !B1_data_in[2];
C1_b[2] = DFFEAS(C1_b[2]_lut_out, clock, rst, , C1L1, , , , );


--C1_a[2] is memory:memory|a[2]
--operation mode is normal

C1_a[2]_lut_out = B1_data_in[2];
C1_a[2] = DFFEAS(C1_a[2]_lut_out, clock, rst, , C1L2, , , , );


--C1L7 is memory:memory|Select~240
--operation mode is normal

C1L7 = B1_mem_read_addr[2] & (B1_mem_read_addr[0]) # !B1_mem_read_addr[2] & (B1_mem_read_addr[0] & !C1_b[2] # !B1_mem_read_addr[0] & (C1_a[2]));


--C1_f[2] is memory:memory|f[2]
--operation mode is normal

C1_f[2]_lut_out = B1_data_in[2];
C1_f[2] = DFFEAS(C1_f[2]_lut_out, clock, VCC, , C1L74, , , , );


--C1L8 is memory:memory|Select~241
--operation mode is normal

C1L8 = B1_mem_read_addr[2] & (C1L7 & (C1_f[2]) # !C1L7 & C1_e[2]) # !B1_mem_read_addr[2] & (C1L7);


--B1L61 is cpu:cpu|Mux~132
--operation mode is normal

B1L61 = D1_instruction[1] & (D1_instruction[0]) # !D1_instruction[1] & (D1_instruction[0] & B1_r[1][2] # !D1_instruction[0] & (B1_r[0][2]));


--B1L71 is cpu:cpu|Mux~133
--operation mode is normal

B1L71 = D1_instruction[1] & (B1L61 & (B1_r[3][2]) # !B1L61 & B1_r[2][2]) # !D1_instruction[1] & (B1L61);


--L3L3 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~26
--operation mode is arithmetic

L3L3_carry_eqn = L3L2;
L3L3 = G1_decoder_node[0][2] $ G1_decoder_node[1][1] $ L3L3_carry_eqn;

--L3L4 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~28
--operation mode is arithmetic

L3L4 = CARRY(G1_decoder_node[0][2] & !G1_decoder_node[1][1] & !L3L2 # !G1_decoder_node[0][2] & (!L3L2 # !G1_decoder_node[1][1]));


--C1_c[3] is memory:memory|c[3]
--operation mode is normal

C1_c[3]_lut_out = B1_data_in[3];
C1_c[3] = DFFEAS(C1_c[3]_lut_out, clock, VCC, , C1L32, , , , );


--C1_d[3] is memory:memory|d[3]
--operation mode is normal

C1_d[3]_lut_out = B1_data_in[3];
C1_d[3] = DFFEAS(C1_d[3]_lut_out, clock, VCC, , C1L92, , , , );


--C1_b[3] is memory:memory|b[3]
--operation mode is normal

C1_b[3]_lut_out = B1_data_in[3];
C1_b[3] = DFFEAS(C1_b[3]_lut_out, clock, rst, , C1L1, , , , );


--C1_e[3] is memory:memory|e[3]
--operation mode is normal

C1_e[3]_lut_out = B1_data_in[3];
C1_e[3] = DFFEAS(C1_e[3]_lut_out, clock, VCC, , C1L14, , , , );


--C1_a[3] is memory:memory|a[3]
--operation mode is normal

C1_a[3]_lut_out = B1_data_in[3];
C1_a[3] = DFFEAS(C1_a[3]_lut_out, clock, rst, , C1L2, , , , );


--C1L9 is memory:memory|Select~242
--operation mode is normal

C1L9 = B1_mem_read_addr[0] & (B1_mem_read_addr[2]) # !B1_mem_read_addr[0] & (B1_mem_read_addr[2] & C1_e[3] # !B1_mem_read_addr[2] & (C1_a[3]));


--C1_f[3] is memory:memory|f[3]
--operation mode is normal

C1_f[3]_lut_out = B1_data_in[3];
C1_f[3] = DFFEAS(C1_f[3]_lut_out, clock, VCC, , C1L74, , , , );


--C1L01 is memory:memory|Select~243
--operation mode is normal

C1L01 = B1_mem_read_addr[0] & (C1L9 & (C1_f[3]) # !C1L9 & C1_b[3]) # !B1_mem_read_addr[0] & (C1L9);


--L3L5 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~31
--operation mode is normal

L3L5_carry_eqn = L3L4;
L3L5 = G1_decoder_node[0][3] $ G1_decoder_node[1][2] $ !L3L5_carry_eqn;


--L6L1 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~7
--operation mode is normal

L6L1 = G1_decoder_node[3][0] $ G1_decoder_node[2][1];


--B1L81 is cpu:cpu|Mux~134
--operation mode is normal

B1L81 = D1_instruction[0] & (D1_instruction[1]) # !D1_instruction[0] & (D1_instruction[1] & B1_r[2][3] # !D1_instruction[1] & (B1_r[0][3]));


--B1L91 is cpu:cpu|Mux~135
--operation mode is normal

B1L91 = D1_instruction[0] & (B1L81 & (B1_r[3][3]) # !B1L81 & B1_r[1][3]) # !D1_instruction[0] & (B1L81);


--B1L731 is cpu:cpu|ram_addr[0]~195
--operation mode is normal

B1L731 = !D1_instruction[10] & !B1L431 & !B1L531 # !D1_instruction[11];


--B1_data_in[0] is cpu:cpu|data_in[0]
--operation mode is normal

B1_data_in[0]_lut_out = B1L9;
B1_data_in[0] = DFFEAS(B1_data_in[0]_lut_out, clock, VCC, , B1L58, , , , );


--B1_mem_write_addr[1] is cpu:cpu|mem_write_addr[1]
--operation mode is normal

B1_mem_write_addr[1]_lut_out = D1_instruction[1];
B1_mem_write_addr[1] = DFFEAS(B1_mem_write_addr[1]_lut_out, clock, VCC, , B1L99, , , , );


--B1_mem_write_addr[0] is cpu:cpu|mem_write_addr[0]
--operation mode is normal

B1_mem_write_addr[0]_lut_out = D1_instruction[0];
B1_mem_write_addr[0] = DFFEAS(B1_mem_write_addr[0]_lut_out, clock, VCC, , B1L99, , , , );


--B1_mem_write_addr[2] is cpu:cpu|mem_write_addr[2]
--operation mode is normal

B1_mem_write_addr[2]_lut_out = D1_instruction[2];
B1_mem_write_addr[2] = DFFEAS(B1_mem_write_addr[2]_lut_out, clock, VCC, , B1L99, , , , );


--C1L32 is memory:memory|c[0]~3
--operation mode is normal

C1L32 = rst & B1_mem_write_addr[1] & !B1_mem_write_addr[0] & !B1_mem_write_addr[2];


--C1L92 is memory:memory|d[0]~3
--operation mode is normal

C1L92 = rst & B1_mem_write_addr[0] & B1_mem_write_addr[1] & !B1_mem_write_addr[2];


--C1L14 is memory:memory|e[0]~3
--operation mode is normal

C1L14 = rst & B1_mem_write_addr[2] & !B1_mem_write_addr[0] & !B1_mem_write_addr[1];


--B1_flag.00 is cpu:cpu|flag.00
--operation mode is normal

B1_flag.00_lut_out = !B1_flag.10;
B1_flag.00 = DFFEAS(B1_flag.00_lut_out, clock, rst, , B1L541, , , , );


--B1L49 is cpu:cpu|mem_read_addr[0]~7
--operation mode is normal

B1L49 = rst & B1L541 & !D1_instruction[8] & !B1_flag.00;


--C1L1 is memory:memory|Decoder~113
--operation mode is normal

C1L1 = B1_mem_write_addr[0] & (!B1_mem_write_addr[1] & !B1_mem_write_addr[2]);


--C1L2 is memory:memory|Decoder~114
--operation mode is normal

C1L2 = !B1_mem_write_addr[0] & !B1_mem_write_addr[1] & !B1_mem_write_addr[2];


--C1L74 is memory:memory|f[0]~3
--operation mode is normal

C1L74 = rst & B1_mem_write_addr[0] & B1_mem_write_addr[2] & !B1_mem_write_addr[1];


--B1_data_in[1] is cpu:cpu|data_in[1]
--operation mode is normal

B1_data_in[1]_lut_out = B1L7;
B1_data_in[1] = DFFEAS(B1_data_in[1]_lut_out, clock, VCC, , B1L58, , , , );


--G1_decoder_node[0][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][1]
--operation mode is normal

G1_decoder_node[0][1] = LCELL(B1L7 & B1L31);


--G1_decoder_node[1][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][0]
--operation mode is normal

G1_decoder_node[1][0] = LCELL(B1L9 & B1L51);


--B1_data_in[2] is cpu:cpu|data_in[2]
--operation mode is normal

B1_data_in[2]_lut_out = B1L11;
B1_data_in[2] = DFFEAS(B1_data_in[2]_lut_out, clock, VCC, , B1L58, , , , );


--G1_decoder_node[2][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[2][0]
--operation mode is normal

G1_decoder_node[2][0] = LCELL(B1L9 & B1L71);


--B1_data_in[3] is cpu:cpu|data_in[3]
--operation mode is normal

B1_data_in[3]_lut_out = B1L5;
B1_data_in[3] = DFFEAS(B1_data_in[3]_lut_out, clock, VCC, , B1L58, , , , );


--G1_decoder_node[3][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[3][0]
--operation mode is normal

G1_decoder_node[3][0] = LCELL(B1L9 & B1L91);


--G1_decoder_node[2][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[2][1]
--operation mode is normal

G1_decoder_node[2][1] = LCELL(B1L7 & B1L71);


--B1L58 is cpu:cpu|data_in[0]~29
--operation mode is normal

B1L58 = D1_instruction[8] & B1_flag.10 & rst & B1L541;


--B1L99 is cpu:cpu|mem_write_addr[0]~37
--operation mode is normal

B1L99 = D1_instruction[8] & rst & B1L541 & !B1_flag.00;


--G1_decoder_node[0][2] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][2]
--operation mode is normal

G1_decoder_node[0][2] = LCELL(B1L11 & B1L31);


--G1_decoder_node[1][1] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][1]
--operation mode is normal

G1_decoder_node[1][1] = LCELL(B1L7 & B1L51);


--G1_decoder_node[0][3] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][3]
--operation mode is normal

G1_decoder_node[0][3] = LCELL(B1L5 & B1L31);


--G1_decoder_node[1][2] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[1][2]
--operation mode is normal

G1_decoder_node[1][2] = LCELL(B1L11 & B1L51);


--B1L601 is cpu:cpu|r[0][1]~1520
--operation mode is normal

B1L601 = !D1_instruction[4] & !D1_instruction[5] & rst & B1L221;


--B1L56 is cpu:cpu|Select~10959
--operation mode is normal

B1L56 = B1_r[0][3] & B1L04 & (D1_instruction[4] # D1_instruction[5]);


--B1L611 is cpu:cpu|r[1][1]~1521
--operation mode is normal

B1L611 = D1_instruction[4] & !D1_instruction[5] & rst & B1L221;


--B1L66 is cpu:cpu|Select~10960
--operation mode is normal

B1L66 = B1_r[1][3] & B1L04 & (D1_instruction[5] # !D1_instruction[4]);


--B1L321 is cpu:cpu|r[2][1]~1522
--operation mode is normal

B1L321 = D1_instruction[5] & !D1_instruction[4] & rst & B1L221;


--B1L76 is cpu:cpu|Select~10961
--operation mode is normal

B1L76 = B1_r[2][3] & B1L04 & (D1_instruction[4] # !D1_instruction[5]);


--B1L921 is cpu:cpu|r[3][1]~1523
--operation mode is normal

B1L921 = D1_instruction[4] & D1_instruction[5] & rst & B1L221;


--B1L86 is cpu:cpu|Select~10962
--operation mode is normal

B1L86 = B1_r[3][3] & B1L04 & (!D1_instruction[5] # !D1_instruction[4]);


--clock is clock
--operation mode is input

clock = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--r0[0] is r0[0]
--operation mode is output

r0[0] = OUTPUT(B1_r[0][0]);


--r0[1] is r0[1]
--operation mode is output

r0[1] = OUTPUT(B1_r[0][1]);


--r0[2] is r0[2]
--operation mode is output

r0[2] = OUTPUT(B1_r[0][2]);


--r0[3] is r0[3]
--operation mode is output

r0[3] = OUTPUT(B1_r[0][3]);


--r1[0] is r1[0]
--operation mode is output

r1[0] = OUTPUT(B1_r[1][0]);


--r1[1] is r1[1]
--operation mode is output

r1[1] = OUTPUT(B1_r[1][1]);


--r1[2] is r1[2]
--operation mode is output

r1[2] = OUTPUT(B1_r[1][2]);


--r1[3] is r1[3]
--operation mode is output

r1[3] = OUTPUT(B1_r[1][3]);


--r2[0] is r2[0]
--operation mode is output

r2[0] = OUTPUT(B1_r[2][0]);


--r2[1] is r2[1]
--operation mode is output

r2[1] = OUTPUT(B1_r[2][1]);


--r2[2] is r2[2]
--operation mode is output

r2[2] = OUTPUT(B1_r[2][2]);


--r2[3] is r2[3]
--operation mode is output

r2[3] = OUTPUT(B1_r[2][3]);


--r3[0] is r3[0]
--operation mode is output

r3[0] = OUTPUT(B1_r[3][0]);


--r3[1] is r3[1]
--operation mode is output

r3[1] = OUTPUT(B1_r[3][1]);


--r3[2] is r3[2]
--operation mode is output

r3[2] = OUTPUT(B1_r[3][2]);


--r3[3] is r3[3]
--operation mode is output

r3[3] = OUTPUT(B1_r[3][3]);


--instruction[0] is instruction[0]
--operation mode is output

instruction[0] = OUTPUT(D1_instruction[0]);


--instruction[1] is instruction[1]
--operation mode is output

instruction[1] = OUTPUT(D1_instruction[1]);


--instruction[2] is instruction[2]
--operation mode is output

instruction[2] = OUTPUT(D1_instruction[2]);


--instruction[3] is instruction[3]
--operation mode is output

instruction[3] = OUTPUT(GND);


--instruction[4] is instruction[4]
--operation mode is output

instruction[4] = OUTPUT(D1_instruction[4]);


--instruction[5] is instruction[5]
--operation mode is output

instruction[5] = OUTPUT(D1_instruction[5]);


--instruction[6] is instruction[6]
--operation mode is output

instruction[6] = OUTPUT(GND);


--instruction[7] is instruction[7]
--operation mode is output

instruction[7] = OUTPUT(GND);


--instruction[8] is instruction[8]
--operation mode is output

instruction[8] = OUTPUT(D1_instruction[8]);


--instruction[9] is instruction[9]
--operation mode is output

instruction[9] = OUTPUT(D1_instruction[9]);


--instruction[10] is instruction[10]
--operation mode is output

instruction[10] = OUTPUT(D1_instruction[10]);


--instruction[11] is instruction[11]
--operation mode is output

instruction[11] = OUTPUT(D1_instruction[11]);