lab5.map.eqn

若若無法引言人元mpeg2 decode

B1L64 = B1L54 # D1_instruction[10] & B1L11 & !D1_instruction[8];


--B1L1 is cpu:cpu|Decoder~172
--operation mode is normal

B1L1 = D1_instruction[4] & (!D1_instruction[5]);


--B1L74 is cpu:cpu|Select~10935
--operation mode is normal

B1L74 = B1L1 & B1L12 # !B1L1 & (B1_r[1][0] & B1L22);


--B1L84 is cpu:cpu|Select~10936
--operation mode is normal

B1L84 = B1L1 & (B1L431 & B1_r[1][0] # !B1L431 & (B1L52)) # !B1L1 & B1_r[1][0];


--B1L94 is cpu:cpu|Select~10937
--operation mode is normal

B1L94 = D1_instruction[11] & (B1L84 & !D1_instruction[8]) # !D1_instruction[11] & B1L74;


--B1L05 is cpu:cpu|Select~10938
--operation mode is normal

B1L05 = B1L1 & (B1L82 # B1L92) # !B1L1 & B1_r[1][0];


--B1L15 is cpu:cpu|Select~10940
--operation mode is normal

B1L15 = B1_flag.10 & (B1L1 & C1_data_out[3] # !B1L1 & (B1_r[1][3])) # !B1_flag.10 & (B1_r[1][3]);


--B1L25 is cpu:cpu|Select~10941
--operation mode is normal

B1L25 = B1L66 # B1L541 & B1L15 & !D1_instruction[8];


--B1L2 is cpu:cpu|Decoder~173
--operation mode is normal

B1L2 = D1_instruction[5] & (!D1_instruction[4]);


--B1L35 is cpu:cpu|Select~10943
--operation mode is normal

B1L35 = B1L2 & B1L12 # !B1L2 & (B1_r[2][0] & B1L22);


--B1L45 is cpu:cpu|Select~10944
--operation mode is normal

B1L45 = B1L2 & (B1L431 & B1_r[2][0] # !B1L431 & (B1L52)) # !B1L2 & B1_r[2][0];


--B1L55 is cpu:cpu|Select~10945
--operation mode is normal

B1L55 = D1_instruction[11] & (B1L45 & !D1_instruction[8]) # !D1_instruction[11] & B1L35;


--B1L65 is cpu:cpu|Select~10946
--operation mode is normal

B1L65 = B1L2 & (B1L82 # B1L92) # !B1L2 & B1_r[2][0];


--B1L75 is cpu:cpu|Select~10948
--operation mode is normal

B1L75 = B1_flag.10 & (B1L2 & C1_data_out[3] # !B1L2 & (B1_r[2][3])) # !B1_flag.10 & (B1_r[2][3]);


--B1L85 is cpu:cpu|Select~10949
--operation mode is normal

B1L85 = B1L76 # B1L541 & B1L75 & !D1_instruction[8];


--B1L3 is cpu:cpu|Decoder~174
--operation mode is normal

B1L3 = D1_instruction[4] & D1_instruction[5];


--B1L95 is cpu:cpu|Select~10951
--operation mode is normal

B1L95 = B1L3 & B1L12 # !B1L3 & (B1_r[3][0] & B1L22);


--B1L06 is cpu:cpu|Select~10952
--operation mode is normal

B1L06 = B1L3 & (B1L431 & B1_r[3][0] # !B1L431 & (B1L52)) # !B1L3 & B1_r[3][0];


--B1L16 is cpu:cpu|Select~10953
--operation mode is normal

B1L16 = D1_instruction[11] & (B1L06 & !D1_instruction[8]) # !D1_instruction[11] & B1L95;


--B1L26 is cpu:cpu|Select~10954
--operation mode is normal

B1L26 = B1L3 & (B1L82 # B1L92) # !B1L3 & B1_r[3][0];


--B1L36 is cpu:cpu|Select~10956
--operation mode is normal

B1L36 = B1_flag.10 & (B1L3 & C1_data_out[3] # !B1L3 & (B1_r[3][3])) # !B1_flag.10 & (B1_r[3][3]);


--B1L46 is cpu:cpu|Select~10957
--operation mode is normal

B1L46 = B1L86 # B1L541 & B1L36 & !D1_instruction[8];


--B1_ram_addr[0] is cpu:cpu|ram_addr[0]
--operation mode is arithmetic

B1_ram_addr[0]_lut_out = !B1_ram_addr[0];
B1_ram_addr[0] = DFFEAS(B1_ram_addr[0]_lut_out, clock, rst, , B1L731, , , , );

--B1L631 is cpu:cpu|ram_addr[0]~176
--operation mode is arithmetic

B1L631 = CARRY(B1_ram_addr[0]);


--B1_ram_addr[1] is cpu:cpu|ram_addr[1]
--operation mode is arithmetic

B1_ram_addr[1]_carry_eqn = B1L631;
B1_ram_addr[1]_lut_out = B1_ram_addr[1] $ (B1_ram_addr[1]_carry_eqn);
B1_ram_addr[1] = DFFEAS(B1_ram_addr[1]_lut_out, clock, rst, , B1L731, , , , );

--B1L931 is cpu:cpu|ram_addr[1]~180
--operation mode is arithmetic

B1L931 = CARRY(!B1L631 # !B1_ram_addr[1]);


--B1_ram_addr[2] is cpu:cpu|ram_addr[2]
--operation mode is arithmetic

B1_ram_addr[2]_carry_eqn = B1L931;
B1_ram_addr[2]_lut_out = B1_ram_addr[2] $ (!B1_ram_addr[2]_carry_eqn);
B1_ram_addr[2] = DFFEAS(B1_ram_addr[2]_lut_out, clock, rst, , B1L731, , , , );

--B1L141 is cpu:cpu|ram_addr[2]~184
--operation mode is arithmetic

B1L141 = CARRY(B1_ram_addr[2] & (!B1L931));


--B1_ram_addr[3] is cpu:cpu|ram_addr[3]
--operation mode is arithmetic

B1_ram_addr[3]_carry_eqn = B1L141;
B1_ram_addr[3]_lut_out = B1_ram_addr[3] $ (B1_ram_addr[3]_carry_eqn);
B1_ram_addr[3] = DFFEAS(B1_ram_addr[3]_lut_out, clock, rst, , B1L731, , , , );

--B1L341 is cpu:cpu|ram_addr[3]~188
--operation mode is arithmetic

B1L341 = CARRY(!B1L141 # !B1_ram_addr[3]);


--D1L11 is prog_ram:prog_ram|reduce_or~405
--operation mode is normal

D1L11 = !B1_ram_addr[0] & (B1_ram_addr[1] & (B1_ram_addr[2] $ !B1_ram_addr[3]) # !B1_ram_addr[1] & !B1_ram_addr[2] & B1_ram_addr[3]);


--B1_ram_addr[4] is cpu:cpu|ram_addr[4]
--operation mode is normal

B1_ram_addr[4]_carry_eqn = B1L341;
B1_ram_addr[4]_lut_out = B1_ram_addr[4] $ (!B1_ram_addr[4]_carry_eqn);
B1_ram_addr[4] = DFFEAS(B1_ram_addr[4]_lut_out, clock, rst, , B1L731, , , , );


--D1L21 is prog_ram:prog_ram|reduce_or~406
--operation mode is normal

D1L21 = !B1_ram_addr[1] & !B1_ram_addr[2] & !B1_ram_addr[3];


--D1L31 is prog_ram:prog_ram|reduce_or~407
--operation mode is normal

D1L31 = B1_ram_addr[4] & (!D1L21 # !B1_ram_addr[0]) # !B1_ram_addr[4] & D1L11;


--D1L41 is prog_ram:prog_ram|reduce_or~408
--operation mode is normal

D1L41 = B1_ram_addr[2] # B1_ram_addr[3] # B1_ram_addr[0] & B1_ram_addr[1];


--D1L51 is prog_ram:prog_ram|reduce_or~409
--operation mode is normal

D1L51 = B1_ram_addr[4] & D1L41;


--D1_instruction[0] is prog_ram:prog_ram|instruction[0]
--operation mode is normal

D1_instruction[0] = D1L51 & (D1_instruction[0]) # !D1L51 & D1L31;


--D1L61 is prog_ram:prog_ram|reduce_or~410
--operation mode is normal

D1L61 = !B1_ram_addr[0] & !B1_ram_addr[1] & !B1_ram_addr[2] & !B1_ram_addr[3];


--D1L71 is prog_ram:prog_ram|reduce_or~411
--operation mode is normal

D1L71 = B1_ram_addr[0] & B1_ram_addr[2] & (B1_ram_addr[1] $ !B1_ram_addr[3]) # !B1_ram_addr[0] & !B1_ram_addr[1] & !B1_ram_addr[2] & B1_ram_addr[3];


--D1L81 is prog_ram:prog_ram|reduce_or~412
--operation mode is normal

D1L81 = B1_ram_addr[4] & D1L61 # !B1_ram_addr[4] & (D1L71);


--D1_instruction[1] is prog_ram:prog_ram|instruction[1]
--operation mode is normal

D1_instruction[1] = D1L51 & (D1_instruction[1]) # !D1L51 & D1L81;


--D1L91 is prog_ram:prog_ram|reduce_or~413
--operation mode is normal

D1L91 = B1_ram_addr[1] & B1_ram_addr[3] & (B1_ram_addr[0] $ B1_ram_addr[2]);


--D1L02 is prog_ram:prog_ram|reduce_or~414
--operation mode is normal

D1L02 = B1_ram_addr[4] & (!D1L61) # !B1_ram_addr[4] & D1L91;


--D1_instruction[2] is prog_ram:prog_ram|instruction[2]
--operation mode is normal

D1_instruction[2] = D1L51 & (D1_instruction[2]) # !D1L51 & D1L02;


--D1L12 is prog_ram:prog_ram|reduce_or~415
--operation mode is normal

D1L12 = B1_ram_addr[1] & (!B1_ram_addr[3] # !B1_ram_addr[2] # !B1_ram_addr[0]) # !B1_ram_addr[1] & (B1_ram_addr[2] # B1_ram_addr[3]);


--D1L22 is prog_ram:prog_ram|reduce_or~416
--operation mode is normal

D1L22 = B1_ram_addr[4] & (!D1L21 # !B1_ram_addr[0]) # !B1_ram_addr[4] & D1L12;


--D1_instruction[4] is prog_ram:prog_ram|instruction[4]
--operation mode is normal

D1_instruction[4] = D1L51 & (D1_instruction[4]) # !D1L51 & D1L22;


--D1_instruction[5] is prog_ram:prog_ram|instruction[5]
--operation mode is normal

D1_instruction[5] = D1L51 & (D1_instruction[5]) # !D1L51 & !D1L61 & B1_ram_addr[4];


--D1L32 is prog_ram:prog_ram|reduce_or~417
--operation mode is normal

D1L32 = B1_ram_addr[0] & (B1_ram_addr[2] $ (B1_ram_addr[1] # B1_ram_addr[3])) # !B1_ram_addr[0] & (B1_ram_addr[3] # !B1_ram_addr[1] & B1_ram_addr[2]);


--D1_instruction[8] is prog_ram:prog_ram|instruction[8]
--operation mode is normal

D1_instruction[8] = D1L51 & (D1_instruction[8]) # !D1L51 & D1L32 & !B1_ram_addr[4];


--D1L42 is prog_ram:prog_ram|reduce_or~418
--operation mode is normal

D1L42 = B1_ram_addr[0] & !B1_ram_addr[1] & (B1_ram_addr[3]) # !B1_ram_addr[0] & B1_ram_addr[1] & (B1_ram_addr[2] $ B1_ram_addr[3]);


--D1_instruction[9] is prog_ram:prog_ram|instruction[9]
--operation mode is normal

D1_instruction[9] = D1L51 & (D1_instruction[9]) # !D1L51 & D1L42 & !B1_ram_addr[4];


--D1L52 is prog_ram:prog_ram|reduce_or~419
--operation mode is normal

D1L52 = B1_ram_addr[0] & B1_ram_addr[2] & (B1_ram_addr[1] $ B1_ram_addr[3]) # !B1_ram_addr[0] & (B1_ram_addr[1] & !B1_ram_addr[2] & B1_ram_addr[3] # !B1_ram_addr[1] & B1_ram_addr[2] & !B1_ram_addr[3]);


--D1_instruction[10] is prog_ram:prog_ram|instruction[10]
--operation mode is normal

D1_instruction[10] = D1L51 & (D1_instruction[10]) # !D1L51 & D1L52 & !B1_ram_addr[4];


--D1L62 is prog_ram:prog_ram|reduce_or~420
--operation mode is normal

D1L62 = B1_ram_addr[0] & (B1_ram_addr[1] $ (!B1_ram_addr[3])) # !B1_ram_addr[0] & (B1_ram_addr[1] & (B1_ram_addr[2] $ !B1_ram_addr[3]) # !B1_ram_addr[1] & !B1_ram_addr[2] & B1_ram_addr[3]);


--D1_instruction[11] is prog_ram:prog_ram|instruction[11]
--operation mode is normal

D1_instruction[11] = D1L51 & (D1_instruction[11]) # !D1L51 & (D1L62 # B1_ram_addr[4]);


--B1L21 is cpu:cpu|Mux~128
--operation mode is normal

B1L21 = D1_instruction[1] & (D1_instruction[0]) # !D1_instruction[1] & (D1_instruction[0] & B1_r[1][0] # !D1_instruction[0] & (B1_r[0][0]));


--B1L31 is cpu:cpu|Mux~129
--operation mode is normal

B1L31 = D1_instruction[1] & (B1L21 & (B1_r[3][0]) # !B1L21 & B1_r[2][0]) # !D1_instruction[1] & (B1L21);


--G1_decoder_node[0][0] is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][0]
--operation mode is normal

G1_decoder_node[0][0] = LCELL(B1L9 & B1L31);


--C1_c[0] is memory:memory|c[0]
--operation mode is normal

C1_c[0]_lut_out = B1_data_in[0];
C1_c[0] = DFFEAS(C1_c[0]_lut_out, clock, VCC, , C1L32, , , , );


--C1_d[0] is memory:memory|d[0]
--operation mode is normal

C1_d[0]_lut_out = B1_data_in[0];
C1_d[0] = DFFEAS(C1_d[0]_lut_out, clock, VCC, , C1L92, , , , );


--C1_e[0] is memory:memory|e[0]
--operation mode is normal

C1_e[0]_lut_out = B1_data_in[0];
C1_e[0] = DFFEAS(C1_e[0]_lut_out, clock, VCC, , C1L14, , , , );


--B1_mem_read_addr[2] is cpu:cpu|mem_read_addr[2]
--operation mode is normal

B1_mem_read_addr[2]_lut_out = D1_instruction[2];
B1_mem_read_addr[2] = DFFEAS(B1_mem_read_addr[2]_lut_out, clock, VCC, , B1L49, , , , );


--C1_b[0] is memory:memory|b[0]
--operation mode is normal

C1_b[0]_lut_out = B1_data_in[0];
C1_b[0] = DFFEAS(C1_b[0]_lut_out, clock, rst, , C1L1, , , , );


--B1_mem_read_addr[0] is cpu:cpu|mem_read_addr[0]
--operation mode is normal

B1_mem_read_addr[0]_lut_out = D1_instruction[0];
B1_mem_read_addr[0] = DFFEAS(B1_mem_read_addr[0]_lut_out, clock, VCC, , B1L49, , , , );


--C1_a[0] is memory:memory|a[0]
--operation mode is normal

C1_a[0]_lut_out = B1_data_in[0];
C1_a[0] = DFFEAS(C1_a[0]_lut_out, clock, rst, , C1L2, , , , );


--C1L3 is memory:memory|Select~236
--operation mode is normal

C1L3 = B1_mem_read_addr[2] & (B1_mem_read_addr[0]) # !B1_mem_read_addr[2] & (B1_mem_read_addr[0] & C1_b[0] # !B1_mem_read_addr[0] & (C1_a[0]));


--C1_f[0] is memory:memory|f[0]
--operation mode is normal

C1_f[0]_lut_out = B1_data_in[0];
C1_f[0] = DFFEAS(C1_f[0]_lut_out, clock, VCC, , C1L74, , , , );


--C1L4 is memory:memory|Select~237
--operation mode is normal

C1L4 = B1_mem_read_addr[2] & (C1L3 & (C1_f[0]) # !C1L3 & C1_e[0]) # !B1_mem_read_addr[2] & (C1L3);


--B1_mem_read_addr[1] is cpu:cpu|mem_read_addr[1]
--operation mode is normal

B1_mem_read_addr[1]_lut_out = D1_instruction[1];
B1_mem_read_addr[1] = DFFEAS(B1_mem_read_addr[1]_lut_out, clock, VCC, , B1L49, , , , );


--C1L53 is memory:memory|data_out[0]~43
--operation mode is normal

C1L53 = rst & (!B1_mem_read_addr[1] # !B1_mem_read_addr[2]);


--B1_flag.01 is cpu:cpu|flag.01
--operation mode is normal

B1_flag.01_lut_out = !B1_flag.00;
B1_flag.01 = DFFEAS(B1_flag.01_lut_out, clock, rst, , B1L541, , , , );


--C1_c[1] is memory:memory|c[1]
--operation mode is normal

C1_c[1]_lut_out = B1_data_in[1];
C1_c[1] = DFFEAS(C1_c[1]_lut_out, clock, VCC, , C1L32, , , , );


--C1_d[1] is memory:memory|d[1]
--operation mode is normal

C1_d[1]_lut_out = B1_data_in[1];
C1_d[1] = DFFEAS(C1_d[1]_lut_out, clock, VCC, , C1L92, , , , );


--C1_e[1] is memory:memory|e[1]
--operation mode is normal

C1_e[1]_lut_out = B1_data_in[1];
C1_e[1] = DFFEAS(C1_e[1]_lut_out, clock, VCC, , C1L14, , , , );


--C1_b[1] is memory:memory|b[1]
--operation mode is normal

C1_b[1]_lut_out = B1_data_in[1];
C1_b[1] = DFFEAS(C1_b[1]_lut_out, clock, rst, , C1L1, , , , );


--C1_a[1] is memory:memory|a[1]
--operation mode is normal

C1_a[1]_lut_out = B1_data_in[1];
C1_a[1] = DFFEAS(C1_a[1]_lut_out, clock, rst, , C1L2, , , , );


--C1L5 is memory:memory|Select~238
--operation mode is normal

C1L5 = B1_mem_read_addr[2] & (B1_mem_read_addr[0]) # !B1_mem_read_addr[2] & (B1_mem_read_addr[0] & C1_b[1] # !B1_mem_read_addr[0] & (C1_a[1]));


--C1_f[1] is memory:memory|f[1]
--operation mode is normal

C1_f[1]_lut_out = B1_data_in[1];
C1_f[1] = DFFEAS(C1_f[1]_lut_out, clock, VCC, , C1L74, , , , );


--C1L6 is memory:memory|Select~239
--operation mode is normal

C1L6 = B1_mem_read_addr[2] & (C1L5 & (C1_f[1]) # !C1L5 & C1_e[1]) # !B1_mem_read_addr[2] & (C1L5);


--B1L41 is cpu:cpu|Mux~130
--operation mode is normal

B1L41 = D1_instruction[0] & (D1_instruction[1]) # !D1_instruction[0] & (D1_instruction[1] & B1_r[2][1] # !D1_instruction[1] & (B1_r[0][1]));


--B1L51 is cpu:cpu|Mux~131
--operation mode is normal

B1L51 = D1_instruction[0] & (B1L41 & (B1_r[3][1]) # !B1L41 & B1_r[1][1]) # !D1_instruction[0] & (B1L41);


--C1_c[2] is memory:memory|c[2]
--operation mode is normal

C1_c[2]_lut_out = B1_data_in[2];
C1_c[2] = DFFEAS(C1_c[2]_lut_out, clock, VCC, , C1L32, , , , );


--C1_d[2] is memory:memory|d[2]
--operation mode is normal

C1_d[2]_lut_out = B1_data_in[2];
C1_d[2] = DFFEAS(C1_d[2]_lut_out, clock, VCC, , C1L92, , , , );


--C1_e[2] is memory:memory|e[2]
--operation mode is normal

C1_e[2]_lut_out = B1_data_in[2];
C1_e[2] = DFFEAS(C1_e[2]_lut_out, clock, VCC, , C1L14, , , , );


--C1_b[2] is memory:memory|b[2]
--operation mode is normal