lab5.map.eqn

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--B1_r[0][0] is cpu:cpu|r[0][0]
--operation mode is normal

B1_r[0][0]_lut_out = D1_instruction[10] & (B1L03 & !D1_instruction[11]) # !D1_instruction[10] & B1L72;
B1_r[0][0] = DFFEAS(B1_r[0][0]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[0][1] is cpu:cpu|r[0][1]
--operation mode is normal

B1_r[0][1]_lut_out = B1L53;
B1_r[0][1] = DFFEAS(B1_r[0][1]_lut_out, clock, VCC, , B1L601, , , , );


--B1_r[0][2] is cpu:cpu|r[0][2]
--operation mode is normal

B1_r[0][2]_lut_out = B1L93;
B1_r[0][2] = DFFEAS(B1_r[0][2]_lut_out, clock, VCC, , B1L601, , , , );


--B1_r[0][3] is cpu:cpu|r[0][3]
--operation mode is normal

B1_r[0][3]_lut_out = B1L24 # B1L32 & B1L64 & !D1_instruction[11];
B1_r[0][3] = DFFEAS(B1_r[0][3]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[1][0] is cpu:cpu|r[1][0]
--operation mode is normal

B1_r[1][0]_lut_out = D1_instruction[10] & (B1L05 & !D1_instruction[11]) # !D1_instruction[10] & B1L94;
B1_r[1][0] = DFFEAS(B1_r[1][0]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[1][1] is cpu:cpu|r[1][1]
--operation mode is normal

B1_r[1][1]_lut_out = B1L53;
B1_r[1][1] = DFFEAS(B1_r[1][1]_lut_out, clock, VCC, , B1L611, , , , );


--B1_r[1][2] is cpu:cpu|r[1][2]
--operation mode is normal

B1_r[1][2]_lut_out = B1L93;
B1_r[1][2] = DFFEAS(B1_r[1][2]_lut_out, clock, VCC, , B1L611, , , , );


--B1_r[1][3] is cpu:cpu|r[1][3]
--operation mode is normal

B1_r[1][3]_lut_out = B1L25 # B1L64 & B1L1 & !D1_instruction[11];
B1_r[1][3] = DFFEAS(B1_r[1][3]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[2][0] is cpu:cpu|r[2][0]
--operation mode is normal

B1_r[2][0]_lut_out = D1_instruction[10] & (B1L65 & !D1_instruction[11]) # !D1_instruction[10] & B1L55;
B1_r[2][0] = DFFEAS(B1_r[2][0]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[2][1] is cpu:cpu|r[2][1]
--operation mode is normal

B1_r[2][1]_lut_out = B1L53;
B1_r[2][1] = DFFEAS(B1_r[2][1]_lut_out, clock, VCC, , B1L321, , , , );


--B1_r[2][2] is cpu:cpu|r[2][2]
--operation mode is normal

B1_r[2][2]_lut_out = B1L93;
B1_r[2][2] = DFFEAS(B1_r[2][2]_lut_out, clock, VCC, , B1L321, , , , );


--B1_r[2][3] is cpu:cpu|r[2][3]
--operation mode is normal

B1_r[2][3]_lut_out = B1L85 # B1L64 & B1L2 & !D1_instruction[11];
B1_r[2][3] = DFFEAS(B1_r[2][3]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[3][0] is cpu:cpu|r[3][0]
--operation mode is normal

B1_r[3][0]_lut_out = D1_instruction[10] & (B1L26 & !D1_instruction[11]) # !D1_instruction[10] & B1L16;
B1_r[3][0] = DFFEAS(B1_r[3][0]_lut_out, clock, VCC, , B1L401, , , , );


--B1_r[3][1] is cpu:cpu|r[3][1]
--operation mode is normal

B1_r[3][1]_lut_out = B1L53;
B1_r[3][1] = DFFEAS(B1_r[3][1]_lut_out, clock, VCC, , B1L921, , , , );


--B1_r[3][2] is cpu:cpu|r[3][2]
--operation mode is normal

B1_r[3][2]_lut_out = B1L93;
B1_r[3][2] = DFFEAS(B1_r[3][2]_lut_out, clock, VCC, , B1L921, , , , );


--B1_r[3][3] is cpu:cpu|r[3][3]
--operation mode is normal

B1_r[3][3]_lut_out = B1L46 # B1L64 & B1L3 & !D1_instruction[11];
B1_r[3][3] = DFFEAS(B1_r[3][3]_lut_out, clock, VCC, , B1L401, , , , );


--B1L96 is cpu:cpu|add~188
--operation mode is arithmetic

B1L96 = B1L9 $ B1L31;

--B1L07 is cpu:cpu|add~190
--operation mode is arithmetic

B1L07 = CARRY(B1L9 # !B1L31);


--B1L02 is cpu:cpu|Select~10906
--operation mode is normal

B1L02 = D1_instruction[8] & G1_decoder_node[0][0] # !D1_instruction[8] & (B1L96);


--B1L17 is cpu:cpu|add~193
--operation mode is arithmetic

B1L17 = B1L9 $ B1L31;

--B1L27 is cpu:cpu|add~195
--operation mode is arithmetic

B1L27 = CARRY(B1L9 & B1L31);


--B1L12 is cpu:cpu|Select~10907
--operation mode is normal

B1L12 = D1_instruction[9] & B1L02 # !D1_instruction[9] & (B1L17 & D1_instruction[8]);


--B1L22 is cpu:cpu|Select~10908
--operation mode is normal

B1L22 = D1_instruction[8] # D1_instruction[9];


--B1L32 is cpu:cpu|Select~10909
--operation mode is normal

B1L32 = !D1_instruction[4] & !D1_instruction[5];


--B1L42 is cpu:cpu|Select~10910
--operation mode is normal

B1L42 = B1L32 & B1L12 # !B1L32 & (B1_r[0][0] & B1L22);


--C1_data_out[0] is memory:memory|data_out[0]
--operation mode is normal

C1_data_out[0]_lut_out = B1_mem_read_addr[0] & (C1_d[0]) # !B1_mem_read_addr[0] & C1_c[0];
C1_data_out[0] = DFFEAS(C1_data_out[0]_lut_out, clock, VCC, , C1L53, C1L4, , , !B1_mem_read_addr[1]);


--B1L52 is cpu:cpu|Select~10911
--operation mode is normal

B1L52 = D1_instruction[9] & D1_instruction[0] # !D1_instruction[9] & (C1_data_out[0]);


--B1_flag.10 is cpu:cpu|flag.10
--operation mode is normal

B1_flag.10_lut_out = B1_flag.01;
B1_flag.10 = DFFEAS(B1_flag.10_lut_out, clock, rst, , B1L541, , , , );


--B1L431 is cpu:cpu|ram_addr[0]~173
--operation mode is normal

B1L431 = !D1_instruction[9] & !B1_flag.10;


--B1L62 is cpu:cpu|Select~10912
--operation mode is normal

B1L62 = B1L32 & (B1L431 & B1_r[0][0] # !B1L431 & (B1L52)) # !B1L32 & B1_r[0][0];


--B1L72 is cpu:cpu|Select~10913
--operation mode is normal

B1L72 = D1_instruction[11] & (B1L62 & !D1_instruction[8]) # !D1_instruction[11] & B1L42;


--B1L4 is cpu:cpu|Mux~120
--operation mode is normal

B1L4 = D1_instruction[4] & (D1_instruction[5]) # !D1_instruction[4] & (D1_instruction[5] & B1_r[2][3] # !D1_instruction[5] & (B1_r[0][3]));


--B1L5 is cpu:cpu|Mux~121
--operation mode is normal

B1L5 = D1_instruction[4] & (B1L4 & (B1_r[3][3]) # !B1L4 & B1_r[1][3]) # !D1_instruction[4] & (B1L4);


--B1L82 is cpu:cpu|Select~10914
--operation mode is normal

B1L82 = D1_instruction[9] & B1L5 & (!D1_instruction[8]);


--B1L6 is cpu:cpu|Mux~122
--operation mode is normal

B1L6 = D1_instruction[5] & (D1_instruction[4]) # !D1_instruction[5] & (D1_instruction[4] & B1_r[1][1] # !D1_instruction[4] & (B1_r[0][1]));


--B1L7 is cpu:cpu|Mux~123
--operation mode is normal

B1L7 = D1_instruction[5] & (B1L6 & (B1_r[3][1]) # !B1L6 & B1_r[2][1]) # !D1_instruction[5] & (B1L6);


--B1L92 is cpu:cpu|Select~10915
--operation mode is normal

B1L92 = D1_instruction[8] & B1L7;


--B1L03 is cpu:cpu|Select~10916
--operation mode is normal

B1L03 = B1L32 & (B1L82 # B1L92) # !B1L32 & B1_r[0][0];


--B1L13 is cpu:cpu|Select~10918
--operation mode is normal

B1L13 = D1_instruction[8] & (D1_instruction[11]) # !D1_instruction[8] & (D1_instruction[10] & (D1_instruction[11]) # !D1_instruction[10] & !D1_instruction[9] & !D1_instruction[11]);


--B1L401 is cpu:cpu|r[0][0]~1514
--operation mode is normal

B1L401 = rst & (!B1L13);


--B1L8 is cpu:cpu|Mux~124
--operation mode is normal

B1L8 = D1_instruction[5] & (D1_instruction[4]) # !D1_instruction[5] & (D1_instruction[4] & B1_r[1][0] # !D1_instruction[4] & (B1_r[0][0]));


--B1L9 is cpu:cpu|Mux~125
--operation mode is normal

B1L9 = D1_instruction[5] & (B1L8 & (B1_r[3][0]) # !B1L8 & B1_r[2][0]) # !D1_instruction[5] & (B1L8);


--B1L801 is cpu:cpu|r[0][2]~1515
--operation mode is normal

B1L801 = D1_instruction[11] & D1_instruction[9] # !D1_instruction[11] & (D1_instruction[10] & !D1_instruction[8]);


--C1_data_out[1] is memory:memory|data_out[1]
--operation mode is normal

C1_data_out[1]_lut_out = B1_mem_read_addr[0] & (C1_d[1]) # !B1_mem_read_addr[0] & C1_c[1];
C1_data_out[1] = DFFEAS(C1_data_out[1]_lut_out, clock, VCC, , C1L53, C1L6, , , !B1_mem_read_addr[1]);


--L3L1 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~21
--operation mode is arithmetic

L3L1 = G1_decoder_node[0][1] $ G1_decoder_node[1][0];

--L3L2 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~23
--operation mode is arithmetic

L3L2 = CARRY(G1_decoder_node[0][1] & G1_decoder_node[1][0]);


--B1L901 is cpu:cpu|r[0][2]~1516
--operation mode is normal

B1L901 = D1_instruction[8] & (D1_instruction[9] # D1_instruction[10]);


--B1L37 is cpu:cpu|add~198
--operation mode is arithmetic

B1L37_carry_eqn = B1L07;
B1L37 = B1L7 $ B1L51 $ !B1L37_carry_eqn;

--B1L47 is cpu:cpu|add~200
--operation mode is arithmetic

B1L47 = CARRY(B1L7 & B1L51 & !B1L07 # !B1L7 & (B1L51 # !B1L07));


--B1L011 is cpu:cpu|r[0][2]~1517
--operation mode is normal

B1L011 = D1_instruction[10] # !D1_instruction[8];


--B1L57 is cpu:cpu|add~203
--operation mode is arithmetic

B1L57_carry_eqn = B1L27;
B1L57 = B1L7 $ B1L51 $ B1L57_carry_eqn;

--B1L67 is cpu:cpu|add~205
--operation mode is arithmetic

B1L67 = CARRY(B1L7 & !B1L51 & !B1L27 # !B1L7 & (!B1L27 # !B1L51));


--B1L23 is cpu:cpu|Select~10919
--operation mode is normal

B1L23 = B1L901 & (B1L011) # !B1L901 & (B1L011 & B1L37 # !B1L011 & (B1L57));


--B1L01 is cpu:cpu|Mux~126
--operation mode is normal

B1L01 = D1_instruction[4] & (D1_instruction[5]) # !D1_instruction[4] & (D1_instruction[5] & B1_r[2][2] # !D1_instruction[5] & (B1_r[0][2]));


--B1L11 is cpu:cpu|Mux~127
--operation mode is normal

B1L11 = D1_instruction[4] & (B1L01 & (B1_r[3][2]) # !B1L01 & B1_r[1][2]) # !D1_instruction[4] & (B1L01);


--B1L33 is cpu:cpu|Select~10920
--operation mode is normal

B1L33 = B1L901 & (B1L23 & (B1L11) # !B1L23 & L3L1) # !B1L901 & (B1L23);


--B1L43 is cpu:cpu|Select~10921
--operation mode is normal

B1L43 = B1L801 & (D1_instruction[11]) # !B1L801 & (D1_instruction[11] & C1_data_out[1] # !D1_instruction[11] & (B1L33));


--B1L53 is cpu:cpu|Select~10922
--operation mode is normal

B1L53 = B1L801 & (B1L43 & (D1_instruction[1]) # !B1L43 & B1L9) # !B1L801 & (B1L43);


--B1L511 is cpu:cpu|r[1][1]~1518
--operation mode is normal

B1L511 = !D1_instruction[8] & !D1_instruction[10];


--B1L221 is cpu:cpu|r[2][1]~1519
--operation mode is normal

B1L221 = B1L511 & (D1_instruction[9] # B1_flag.10 & D1_instruction[11]) # !B1L511 & (!D1_instruction[11]);


--C1_data_out[2] is memory:memory|data_out[2]
--operation mode is normal

C1_data_out[2]_lut_out = B1_mem_read_addr[0] & (C1_d[2]) # !B1_mem_read_addr[0] & C1_c[2];
C1_data_out[2] = DFFEAS(C1_data_out[2]_lut_out, clock, VCC, , C1L53, C1L8, , , !B1_mem_read_addr[1]);


--B1L77 is cpu:cpu|add~208
--operation mode is arithmetic

B1L77_carry_eqn = B1L47;
B1L77 = B1L11 $ B1L71 $ B1L77_carry_eqn;

--B1L87 is cpu:cpu|add~210
--operation mode is arithmetic

B1L87 = CARRY(B1L11 & (!B1L47 # !B1L71) # !B1L11 & !B1L71 & !B1L47);


--L9L1 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~14
--operation mode is arithmetic

L9L1 = L3L3 $ G1_decoder_node[2][0];

--L9L2 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~16
--operation mode is arithmetic

L9L2 = CARRY(L3L3 & G1_decoder_node[2][0]);


--B1L97 is cpu:cpu|add~213
--operation mode is arithmetic

B1L97_carry_eqn = B1L67;
B1L97 = B1L11 $ B1L71 $ !B1L97_carry_eqn;

--B1L08 is cpu:cpu|add~215
--operation mode is arithmetic

B1L08 = CARRY(B1L11 & (B1L71 # !B1L67) # !B1L11 & B1L71 & !B1L67);


--B1L63 is cpu:cpu|Select~10923
--operation mode is normal

B1L63 = B1L011 & (B1L901) # !B1L011 & (B1L901 & L9L1 # !B1L901 & (B1L97));


--B1L73 is cpu:cpu|Select~10924
--operation mode is normal

B1L73 = B1L011 & (B1L63 & (B1L5) # !B1L63 & B1L77) # !B1L011 & (B1L63);


--B1L83 is cpu:cpu|Select~10925
--operation mode is normal

B1L83 = B1L801 & (D1_instruction[11]) # !B1L801 & (D1_instruction[11] & C1_data_out[2] # !D1_instruction[11] & (B1L73));


--B1L93 is cpu:cpu|Select~10926
--operation mode is normal

B1L93 = B1L801 & (B1L83 & (D1_instruction[2]) # !B1L83 & B1L7) # !B1L801 & (B1L83);


--B1L04 is cpu:cpu|Select~10927
--operation mode is normal

B1L04 = D1_instruction[8] & (!D1_instruction[11]) # !D1_instruction[8] & (D1_instruction[10] & (!D1_instruction[11]) # !D1_instruction[10] & D1_instruction[9]);


--C1_data_out[3] is memory:memory|data_out[3]
--operation mode is normal

C1_data_out[3]_lut_out = B1_mem_read_addr[0] & (C1_d[3]) # !B1_mem_read_addr[0] & C1_c[3];
C1_data_out[3] = DFFEAS(C1_data_out[3]_lut_out, clock, VCC, , C1L53, C1L01, , , !B1_mem_read_addr[1]);


--B1L14 is cpu:cpu|Select~10928
--operation mode is normal

B1L14 = B1L32 & (B1_flag.10 & C1_data_out[3] # !B1_flag.10 & (B1_r[0][3])) # !B1L32 & (B1_r[0][3]);


--B1L541 is cpu:cpu|reduce_or~18
--operation mode is normal

B1L541 = D1_instruction[11] & (!D1_instruction[9] & !D1_instruction[10]);


--B1L24 is cpu:cpu|Select~10929
--operation mode is normal

B1L24 = B1L56 # B1L14 & B1L541 & !D1_instruction[8];


--B1L531 is cpu:cpu|ram_addr[0]~174
--operation mode is normal

B1L531 = D1_instruction[8] & D1_instruction[9];


--L9L3 is cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~19
--operation mode is normal

L9L3_carry_eqn = L9L2;
L9L3 = L3L5 $ L6L1 $ L9L3_carry_eqn;


--B1L18 is cpu:cpu|add~218
--operation mode is normal

B1L18_carry_eqn = B1L08;
B1L18 = B1L5 $ B1L91 $ B1L18_carry_eqn;


--B1L34 is cpu:cpu|Select~10930
--operation mode is normal

B1L34 = D1_instruction[9] & L9L3 # !D1_instruction[9] & (B1L18);


--B1L28 is cpu:cpu|add~223
--operation mode is normal

B1L28_carry_eqn = B1L87;
B1L28 = B1L5 $ B1L91 $ !B1L28_carry_eqn;


--B1L44 is cpu:cpu|Select~10931
--operation mode is normal

B1L44 = D1_instruction[8] & B1L34 # !D1_instruction[8] & (B1L28 & D1_instruction[9]);


--B1L54 is cpu:cpu|Select~10932
--operation mode is normal

B1L54 = D1_instruction[10] & B1L9 & B1L531 # !D1_instruction[10] & (B1L44);


--B1L64 is cpu:cpu|Select~10933
--operation mode is normal