lab2_sim.v

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module lab2_sim (clock,rst,r0,r1,r2,r3,instruction);
 wire [3:0] data_in,data_out,mem_read_addr,mem_write_addr;
 wire [4:0] ram_addr;
 wire [11:0] instruction;
 input clock,rst; 
 wire	[3:0]r0,r1,r2,r3;
 output	[3:0]r0,r1,r2,r3;
 output [11:0] instruction;
 cpu cpu (ram_addr,mem_read_addr,mem_write_addr,data_out,instruction,data_in,clock,rst,r0,r1,r2,r3);
 memory memory (data_in,data_out,mem_write_addr,mem_read_addr,clock,rst); 
 prog_ram prog_ram (instruction,ram_addr);
 
 /*initial
 begin
 clock=0;
 rst=1;
 end
 
 always
 #10 clock=~clock;
 
 always
 #1 rst=0;
*/
   
endmodule