lab5.fit.qmsg

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{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "28 unused 3.30 0 28 0 " "Info: Number of I/O pins in group: 28 (unused VREF, 3.30 VCCIO, 0 input, 28 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 29 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 30 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 51 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 51 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 2 27 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  27 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 29 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 52 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 51 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.191 ns register register " "Info: Estimated most critical path is register to register delay of 10.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cpu:cpu\|ram_addr\[0\] 1 REG LAB_X24_Y24 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y24; Fanout = 15; REG Node = 'cpu:cpu\|ram_addr\[0\]'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { cpu:cpu|ram_addr[0] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.320 ns) + CELL(0.366 ns) 0.686 ns prog_ram:prog_ram\|reduce_or~410 2 COMB LAB_X25_Y24 4 " "Info: 2: + IC(0.320 ns) + CELL(0.366 ns) = 0.686 ns; Loc. = LAB_X25_Y24; Fanout = 4; COMB Node = 'prog_ram:prog_ram\|reduce_or~410'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.686 ns" { cpu:cpu|ram_addr[0] prog_ram:prog_ram|reduce_or~410 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.366 ns) 1.154 ns prog_ram:prog_ram\|reduce_or~412 3 COMB LAB_X25_Y24 2 " "Info: 3: + IC(0.102 ns) + CELL(0.366 ns) = 1.154 ns; Loc. = LAB_X25_Y24; Fanout = 2; COMB Node = 'prog_ram:prog_ram\|reduce_or~412'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { prog_ram:prog_ram|reduce_or~410 prog_ram:prog_ram|reduce_or~412 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.280 ns) 2.519 ns prog_ram:prog_ram\|instruction\[1\] 4 COMB LAB_X30_Y26 12 " "Info: 4: + IC(1.085 ns) + CELL(0.280 ns) = 2.519 ns; Loc. = LAB_X30_Y26; Fanout = 12; COMB Node = 'prog_ram:prog_ram\|instruction\[1\]'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.365 ns" { prog_ram:prog_ram|reduce_or~412 prog_ram:prog_ram|instruction[1] } "NODE_NAME" } "" } } { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.366 ns) 3.612 ns cpu:cpu\|Mux~128 5 COMB LAB_X31_Y27 1 " "Info: 5: + IC(0.727 ns) + CELL(0.366 ns) = 3.612 ns; Loc. = LAB_X31_Y27; Fanout = 1; COMB Node = 'cpu:cpu\|Mux~128'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.093 ns" { prog_ram:prog_ram|instruction[1] cpu:cpu|Mux~128 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.183 ns) 4.080 ns cpu:cpu\|Mux~129 6 COMB LAB_X31_Y27 10 " "Info: 6: + IC(0.285 ns) + CELL(0.183 ns) = 4.080 ns; Loc. = LAB_X31_Y27; Fanout = 10; COMB Node = 'cpu:cpu\|Mux~129'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { cpu:cpu|Mux~128 cpu:cpu|Mux~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.188 ns) + CELL(0.280 ns) 4.548 ns cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|decoder_node\[0\]\[1\] 7 COMB LAB_X31_Y27 3 " "Info: 7: + IC(0.188 ns) + CELL(0.280 ns) = 4.548 ns; Loc. = LAB_X31_Y27; Fanout = 3; COMB Node = 'cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|decoder_node\[0\]\[1\]'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { cpu:cpu|Mux~129 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][1] } "NODE_NAME" } "" } } { "multcore.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/multcore.tdf" 251 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.451 ns) 5.950 ns cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~23COUT1 8 COMB LAB_X30_Y24 2 " "Info: 8: + IC(0.951 ns) + CELL(0.451 ns) = 5.950 ns; Loc. = LAB_X30_Y24; Fanout = 2; COMB Node = 'cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~23COUT1'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.402 ns" { cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][1] cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~23COUT1 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 6.315 ns cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~26 9 COMB LAB_X30_Y24 3 " "Info: 9: + IC(0.000 ns) + CELL(0.365 ns) = 6.315 ns; Loc. = LAB_X30_Y24; Fanout = 3; COMB Node = 'cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~26'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.365 ns" { cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~23COUT1 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~26 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.366 ns) 6.982 ns cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~14 10 COMB LAB_X30_Y24 1 " "Info: 10: + IC(0.301 ns) + CELL(0.366 ns) = 6.982 ns; Loc. = LAB_X30_Y24; Fanout = 1; COMB Node = 'cpu:cpu\|lpm_mult:mult_rtl_0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~14'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.667 ns" { cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~26 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~14 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50sp1/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.280 ns) 8.100 ns cpu:cpu\|Select~10923 11 COMB LAB_X30_Y27 1 " "Info: 11: + IC(0.838 ns) + CELL(0.280 ns) = 8.100 ns; Loc. = LAB_X30_Y27; Fanout = 1; COMB Node = 'cpu:cpu\|Select~10923'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.118 ns" { cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~14 cpu:cpu|Select~10923 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.183 ns) 8.568 ns cpu:cpu\|Select~10924 12 COMB LAB_X30_Y27 1 " "Info: 12: + IC(0.285 ns) + CELL(0.183 ns) = 8.568 ns; Loc. = LAB_X30_Y27; Fanout = 1; COMB Node = 'cpu:cpu\|Select~10924'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { cpu:cpu|Select~10923 cpu:cpu|Select~10924 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.075 ns) 9.036 ns cpu:cpu\|Select~10925 13 COMB LAB_X30_Y27 2 " "Info: 13: + IC(0.393 ns) + CELL(0.075 ns) = 9.036 ns; Loc. = LAB_X30_Y27; Fanout = 2; COMB Node = 'cpu:cpu\|Select~10925'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { cpu:cpu|Select~10924 cpu:cpu|Select~10925 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.183 ns) 9.504 ns cpu:cpu\|Select~10926 14 COMB LAB_X30_Y27 3 " "Info: 14: + IC(0.285 ns) + CELL(0.183 ns) = 9.504 ns; Loc. = LAB_X30_Y27; Fanout = 3; COMB Node = 'cpu:cpu\|Select~10926'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.468 ns" { cpu:cpu|Select~10925 cpu:cpu|Select~10926 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.085 ns) 10.191 ns cpu:cpu\|r\[2\]\[2\] 15 REG LAB_X29_Y27 3 " "Info: 15: + IC(0.602 ns) + CELL(0.085 ns) = 10.191 ns; Loc. = LAB_X29_Y27; Fanout = 3; REG Node = 'cpu:cpu\|r\[2\]\[2\]'" {  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.687 ns" { cpu:cpu|Select~10926 cpu:cpu|r[2][2] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.829 ns 37.57 % " "Info: Total cell delay = 3.829 ns ( 37.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.362 ns 62.43 % " "Info: Total interconnect delay = 6.362 ns ( 62.43 % )" {  } {  } 0}  } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "10.191 ns" { cpu:cpu|ram_addr[0] prog_ram:prog_ram|reduce_or~410 prog_ram:prog_ram|reduce_or~412 prog_ram:prog_ram|instruction[1] cpu:cpu|Mux~128 cpu:cpu|Mux~129 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|decoder_node[0][1] cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~23COUT1 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~26 cpu:cpu|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~14 cpu:cpu|Select~10923 cpu:cpu|Select~10924 cpu:cpu|Select~10925 cpu:cpu|Select~10926 cpu:cpu|r[2][2] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}