lab5.fit.qmsg

若若無法引言人元mpeg2 decode

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clock Global clock in PIN L2 " "Info: Automatically promoted signal \"clock\" to use Global clock in PIN L2" {  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "prog_ram:prog_ram\|reduce_or~409 Global clock " "Info: Automatically promoted signal \"prog_ram:prog_ram\|reduce_or~409\" to use Global clock" {  } { { "c:/altera/quartus50sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50sp1/bin/Assignment Editor.qase" 1 { { 0 "prog_ram:prog_ram\|reduce_or~409" } } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { prog_ram:prog_ram|reduce_or~409 } "NODE_NAME" } "" } } { "C:/altera/lab5/lab5.fld" "" { Floorplan "C:/altera/lab5/lab5.fld" "" "" { prog_ram:prog_ram|reduce_or~409 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock in PIN L3 " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock in PIN L3" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cpu:cpu\|r\[0\]\[0\]~1514 " "Info: Destination \"cpu:cpu\|r\[0\]\[0\]~1514\" may be non-global or may not use global clock" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "memory:memory\|data_out\[0\]~43 " "Info: Destination \"memory:memory\|data_out\[0\]~43\" may be non-global or may not use global clock" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "memory:memory\|c\[0\]~3 " "Info: Destination \"memory:memory\|c\[0\]~3\" may be non-global or may not use global clock" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "memory:memory\|d\[0\]~3 " "Info: Destination \"memory:memory\|d\[0\]~3\" may be non-global or may not use global clock" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "memory:memory\|e\[0\]~3 " "Info: Destination \"memory:memory\|e\[0\]~3\" may be non-global or may not use global clock" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cpu:cpu\|mem_read_addr\[0\]~7 " "Info: Destination \"cpu:cpu\|mem_read_addr\[0\]~7\" may be non-global or may not use global clock" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 4 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "memory:memory\|f\[0\]~3 " "Info: Destination \"memory:memory\|f\[0\]~3\" may be non-global or may not use global clock" {  } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cpu:cpu\|data_in\[0\]~29 " "Info: Destination \"cpu:cpu\|data_in\[0\]~29\" may be non-global or may not use global clock" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 4 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cpu:cpu\|mem_write_addr\[0\]~37 " "Info: Destination \"cpu:cpu\|mem_write_addr\[0\]~37\" may be non-global or may not use global clock" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 4 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cpu:cpu\|r\[0\]\[1\]~1520 " "Info: Destination \"cpu:cpu\|r\[0\]\[1\]~1520\" may be non-global or may not use global clock" {  } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}