📄 lab5.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register cpu:cpu\|ram_addr\[3\] register cpu:cpu\|r\[0\]\[3\] 66.63 MHz 15.009 ns Internal " "Info: Clock \"clock\" has Internal fmax of 66.63 MHz between source register \"cpu:cpu\|ram_addr\[3\]\" and destination register \"cpu:cpu\|r\[0\]\[3\]\" (period= 15.009 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.812 ns + Longest register register " "Info: + Longest register to register delay is 14.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cpu:cpu\|ram_addr\[3\] 1 REG LC_X24_Y24_N3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y24_N3; Fanout = 14; REG Node = 'cpu:cpu\|ram_addr\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.366 ns) 0.792 ns prog_ram:prog_ram\|reduce_or~408 2 COMB LC_X24_Y24_N6 1 " "Info: 2: + IC(0.426 ns) + CELL(0.366 ns) = 0.792 ns; Loc. = LC_X24_Y24_N6; Fanout = 1; COMB Node = 'prog_ram:prog_ram\|reduce_or~408'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.792 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 1.001 ns prog_ram:prog_ram\|reduce_or~409 3 COMB LC_X24_Y24_N7 18 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 1.001 ns; Loc. = LC_X24_Y24_N7; Fanout = 18; COMB Node = 'prog_ram:prog_ram\|reduce_or~409'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.209 ns" { prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.905 ns) 4.906 ns prog_ram:prog_ram\|instruction\[4\] 4 COMB LOOP LC_X31_Y27_N9 21 " "Info: 4: + IC(0.000 ns) + CELL(3.905 ns) = 4.906 ns; Loc. = LC_X31_Y27_N9; Fanout = 21; COMB LOOP Node = 'prog_ram:prog_ram\|instruction\[4\]'" { { "Info" "ITDB_PART_OF_SCC" "prog_ram:prog_ram\|instruction\[4\] LC_X31_Y27_N9 " "Info: Loc. = LC_X31_Y27_N9; Node \"prog_ram:prog_ram\|instruction\[4\]\"" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { prog_ram:prog_ram|instruction[4] } "NODE_NAME" } "" } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { prog_ram:prog_ram|instruction[4] } "NODE_NAME" } "" } } { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "3.905 ns" { prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[4] } "NODE_NAME" } "" } } { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.366 ns) 7.097 ns cpu:cpu\|Mux~126 5 COMB LC_X29_Y27_N5 1 " "Info: 5: + IC(1.825 ns) + CELL(0.366 ns) = 7.097 ns; Loc. = LC_X29_Y27_N5; Fanout = 1; COMB Node = 'cpu:cpu\|Mux~126'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.191 ns" { prog_ram:prog_ram|instruction[4] cpu:cpu|Mux~126 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.280 ns) 8.146 ns cpu:cpu\|Mux~127 6 COMB LC_X31_Y27_N2 11 " "Info: 6: + IC(0.769 ns) + CELL(0.280 ns) = 8.146 ns; Loc. = LC_X31_Y27_N2; Fanout = 11; COMB Node = 'cpu:cpu\|Mux~127'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.049 ns" { cpu:cpu|Mux~126 cpu:cpu|Mux~127 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.940 ns) + CELL(0.451 ns) 10.537 ns cpu:cpu\|add~215COUT1_232 7 COMB LC_X30_Y27_N7 1 " "Info: 7: + IC(1.940 ns) + CELL(0.451 ns) = 10.537 ns; Loc. = LC_X30_Y27_N7; Fanout = 1; COMB Node = 'cpu:cpu\|add~215COUT1_232'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.391 ns" { cpu:cpu|Mux~127 cpu:cpu|add~215COUT1_232 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 10.902 ns cpu:cpu\|add~218 8 COMB LC_X30_Y27_N8 1 " "Info: 8: + IC(0.000 ns) + CELL(0.365 ns) = 10.902 ns; Loc. = LC_X30_Y27_N8; Fanout = 1; COMB Node = 'cpu:cpu\|add~218'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.365 ns" { cpu:cpu|add~215COUT1_232 cpu:cpu|add~218 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.008 ns) + CELL(0.183 ns) 12.093 ns cpu:cpu\|Select~10930 9 COMB LC_X30_Y24_N4 1 " "Info: 9: + IC(1.008 ns) + CELL(0.183 ns) = 12.093 ns; Loc. = LC_X30_Y24_N4; Fanout = 1; COMB Node = 'cpu:cpu\|Select~10930'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.191 ns" { cpu:cpu|add~218 cpu:cpu|Select~10930 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.075 ns) 12.490 ns cpu:cpu\|Select~10931 10 COMB LC_X30_Y24_N0 1 " "Info: 10: + IC(0.322 ns) + CELL(0.075 ns) = 12.490 ns; Loc. = LC_X30_Y24_N0; Fanout = 1; COMB Node = 'cpu:cpu\|Select~10931'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.397 ns" { cpu:cpu|Select~10930 cpu:cpu|Select~10931 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.316 ns) + CELL(0.075 ns) 12.881 ns cpu:cpu\|Select~10932 11 COMB LC_X30_Y24_N3 1 " "Info: 11: + IC(0.316 ns) + CELL(0.075 ns) = 12.881 ns; Loc. = LC_X30_Y24_N3; Fanout = 1; COMB Node = 'cpu:cpu\|Select~10932'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.391 ns" { cpu:cpu|Select~10931 cpu:cpu|Select~10932 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.366 ns) 13.573 ns cpu:cpu\|Select~10933 12 COMB LC_X30_Y24_N9 4 " "Info: 12: + IC(0.326 ns) + CELL(0.366 ns) = 13.573 ns; Loc. = LC_X30_Y24_N9; Fanout = 4; COMB Node = 'cpu:cpu\|Select~10933'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.692 ns" { cpu:cpu|Select~10932 cpu:cpu|Select~10933 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.458 ns) 14.812 ns cpu:cpu\|r\[0\]\[3\] 13 REG LC_X31_Y24_N5 5 " "Info: 13: + IC(0.781 ns) + CELL(0.458 ns) = 14.812 ns; Loc. = LC_X31_Y24_N5; Fanout = 5; REG Node = 'cpu:cpu\|r\[0\]\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.239 ns" { cpu:cpu|Select~10933 cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.965 ns 47.02 % " "Info: Total cell delay = 6.965 ns ( 47.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.847 ns 52.98 % " "Info: Total interconnect delay = 7.847 ns ( 52.98 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "14.812 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[4] cpu:cpu|Mux~126 cpu:cpu|Mux~127 cpu:cpu|add~215COUT1_232 cpu:cpu|add~218 cpu:cpu|Select~10930 cpu:cpu|Select~10931 cpu:cpu|Select~10932 cpu:cpu|Select~10933 cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "14.812 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[4] cpu:cpu|Mux~126 cpu:cpu|Mux~127 cpu:cpu|add~215COUT1_232 cpu:cpu|add~218 cpu:cpu|Select~10930 cpu:cpu|Select~10931 cpu:cpu|Select~10932 cpu:cpu|Select~10933 cpu:cpu|r[0][3] } { 0.000ns 0.426ns 0.134ns 0.000ns 1.825ns 0.769ns 1.940ns 0.000ns 1.008ns 0.322ns 0.316ns 0.326ns 0.781ns } { 0.000ns 0.366ns 0.075ns 3.905ns 0.366ns 0.280ns 0.451ns 0.365ns 0.183ns 0.075ns 0.075ns 0.366ns 0.458ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.031 ns - Smallest " "Info: - Smallest clock skew is -0.031 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.788 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 62 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 62; CLK Node = 'clock'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { clock } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.521 ns) + CELL(0.542 ns) 2.788 ns cpu:cpu\|r\[0\]\[3\] 2 REG LC_X31_Y24_N5 5 " "Info: 2: + IC(1.521 ns) + CELL(0.542 ns) = 2.788 ns; Loc. = LC_X31_Y24_N5; Fanout = 5; REG Node = 'cpu:cpu\|r\[0\]\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.063 ns" { clock cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.44 % " "Info: Total cell delay = 1.267 ns ( 45.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.521 ns 54.56 % " "Info: Total interconnect delay = 1.521 ns ( 54.56 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.788 ns" { clock cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 cpu:cpu|r[0][3] } { 0.000ns 0.000ns 1.521ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.819 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 62 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 62; CLK Node = 'clock'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { clock } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.819 ns cpu:cpu\|ram_addr\[3\] 2 REG LC_X24_Y24_N3 14 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.819 ns; Loc. = LC_X24_Y24_N3; Fanout = 14; REG Node = 'cpu:cpu\|ram_addr\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.094 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.95 % " "Info: Total cell delay = 1.267 ns ( 44.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns 55.05 % " "Info: Total interconnect delay = 1.552 ns ( 55.05 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.819 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.819 ns" { clock clock~out0 cpu:cpu|ram_addr[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.725ns 0.542ns } } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.788 ns" { clock cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 cpu:cpu|r[0][3] } { 0.000ns 0.000ns 1.521ns } { 0.000ns 0.725ns 0.542ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.819 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.819 ns" { clock clock~out0 cpu:cpu|ram_addr[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "14.812 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[4] cpu:cpu|Mux~126 cpu:cpu|Mux~127 cpu:cpu|add~215COUT1_232 cpu:cpu|add~218 cpu:cpu|Select~10930 cpu:cpu|Select~10931 cpu:cpu|Select~10932 cpu:cpu|Select~10933 cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "14.812 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[4] cpu:cpu|Mux~126 cpu:cpu|Mux~127 cpu:cpu|add~215COUT1_232 cpu:cpu|add~218 cpu:cpu|Select~10930 cpu:cpu|Select~10931 cpu:cpu|Select~10932 cpu:cpu|Select~10933 cpu:cpu|r[0][3] } { 0.000ns 0.426ns 0.134ns 0.000ns 1.825ns 0.769ns 1.940ns 0.000ns 1.008ns 0.322ns 0.316ns 0.326ns 0.781ns } { 0.000ns 0.366ns 0.075ns 3.905ns 0.366ns 0.280ns 0.451ns 0.365ns 0.183ns 0.075ns 0.075ns 0.366ns 0.458ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.788 ns" { clock cpu:cpu|r[0][3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 cpu:cpu|r[0][3] } { 0.000ns 0.000ns 1.521ns } { 0.000ns 0.725ns 0.542ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.819 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.819 ns" { clock clock~out0 cpu:cpu|ram_addr[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.725ns 0.542ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "cpu:cpu\|r\[0\]\[1\] rst clock 2.194 ns register " "Info: tsu for register \"cpu:cpu\|r\[0\]\[1\]\" (data pin = \"rst\", clock pin = \"clock\") is 2.194 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.984 ns + Longest pin register " "Info: + Longest pin to register delay is 4.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns rst 1 PIN PIN_L3 29 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 29; PIN Node = 'rst'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { rst } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.942 ns) + CELL(0.280 ns) 3.050 ns cpu:cpu\|r\[0\]\[1\]~1520 2 COMB LC_X29_Y27_N1 2 " "Info: 2: + IC(1.942 ns) + CELL(0.280 ns) = 3.050 ns; Loc. = LC_X29_Y27_N1; Fanout = 2; COMB Node = 'cpu:cpu\|r\[0\]\[1\]~1520'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.222 ns" { rst cpu:cpu|r[0][1]~1520 } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.229 ns) + CELL(0.705 ns) 4.984 ns cpu:cpu\|r\[0\]\[1\] 3 REG LC_X31_Y26_N5 3 " "Info: 3: + IC(1.229 ns) + CELL(0.705 ns) = 4.984 ns; Loc. = LC_X31_Y26_N5; Fanout = 3; REG Node = 'cpu:cpu\|r\[0\]\[1\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.934 ns" { cpu:cpu|r[0][1]~1520 cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.813 ns 36.38 % " "Info: Total cell delay = 1.813 ns ( 36.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.171 ns 63.62 % " "Info: Total interconnect delay = 3.171 ns ( 63.62 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "4.984 ns" { rst cpu:cpu|r[0][1]~1520 cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "4.984 ns" { rst rst~out0 cpu:cpu|r[0][1]~1520 cpu:cpu|r[0][1] } { 0.000ns 0.000ns 1.942ns 1.229ns } { 0.000ns 0.828ns 0.280ns 0.705ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 62 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 62; CLK Node = 'clock'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { clock } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.542 ns) 2.800 ns cpu:cpu\|r\[0\]\[1\] 2 REG LC_X31_Y26_N5 3 " "Info: 2: + IC(1.533 ns) + CELL(0.542 ns) = 2.800 ns; Loc. = LC_X31_Y26_N5; Fanout = 3; REG Node = 'cpu:cpu\|r\[0\]\[1\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.075 ns" { clock cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.25 % " "Info: Total cell delay = 1.267 ns ( 45.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns 54.75 % " "Info: Total interconnect delay = 1.533 ns ( 54.75 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.800 ns" { clock cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.800 ns" { clock clock~out0 cpu:cpu|r[0][1] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.725ns 0.542ns } } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "4.984 ns" { rst cpu:cpu|r[0][1]~1520 cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "4.984 ns" { rst rst~out0 cpu:cpu|r[0][1]~1520 cpu:cpu|r[0][1] } { 0.000ns 0.000ns 1.942ns 1.229ns } { 0.000ns 0.828ns 0.280ns 0.705ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.800 ns" { clock cpu:cpu|r[0][1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.800 ns" { clock clock~out0 cpu:cpu|r[0][1] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.725ns 0.542ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock instruction\[1\] cpu:cpu\|ram_addr\[3\] 12.264 ns register " "Info: tco from clock \"clock\" to destination pin \"instruction\[1\]\" through register \"cpu:cpu\|ram_addr\[3\]\" is 12.264 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.819 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 62 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 62; CLK Node = 'clock'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { clock } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.552 ns) + CELL(0.542 ns) 2.819 ns cpu:cpu\|ram_addr\[3\] 2 REG LC_X24_Y24_N3 14 " "Info: 2: + IC(1.552 ns) + CELL(0.542 ns) = 2.819 ns; Loc. = LC_X24_Y24_N3; Fanout = 14; REG Node = 'cpu:cpu\|ram_addr\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.094 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.95 % " "Info: Total cell delay = 1.267 ns ( 44.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.552 ns 55.05 % " "Info: Total interconnect delay = 1.552 ns ( 55.05 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.819 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.819 ns" { clock clock~out0 cpu:cpu|ram_addr[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.289 ns + Longest register pin " "Info: + Longest register to pin delay is 9.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cpu:cpu\|ram_addr\[3\] 1 REG LC_X24_Y24_N3 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y24_N3; Fanout = 14; REG Node = 'cpu:cpu\|ram_addr\[3\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "cpu.v" "" { Text "C:/altera/lab5/cpu.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.366 ns) 0.792 ns prog_ram:prog_ram\|reduce_or~408 2 COMB LC_X24_Y24_N6 1 " "Info: 2: + IC(0.426 ns) + CELL(0.366 ns) = 0.792 ns; Loc. = LC_X24_Y24_N6; Fanout = 1; COMB Node = 'prog_ram:prog_ram\|reduce_or~408'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.792 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 1.001 ns prog_ram:prog_ram\|reduce_or~409 3 COMB LC_X24_Y24_N7 18 " "Info: 3: + IC(0.134 ns) + CELL(0.075 ns) = 1.001 ns; Loc. = LC_X24_Y24_N7; Fanout = 18; COMB Node = 'prog_ram:prog_ram\|reduce_or~409'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "0.209 ns" { prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.773 ns) 4.774 ns prog_ram:prog_ram\|instruction\[1\] 4 COMB LOOP LC_X30_Y26_N0 12 " "Info: 4: + IC(0.000 ns) + CELL(3.773 ns) = 4.774 ns; Loc. = LC_X30_Y26_N0; Fanout = 12; COMB LOOP Node = 'prog_ram:prog_ram\|instruction\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "prog_ram:prog_ram\|instruction\[1\] LC_X30_Y26_N0 " "Info: Loc. = LC_X30_Y26_N0; Node \"prog_ram:prog_ram\|instruction\[1\]\"" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { prog_ram:prog_ram|instruction[1] } "NODE_NAME" } "" } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { prog_ram:prog_ram|instruction[1] } "NODE_NAME" } "" } } { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "3.773 ns" { prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[1] } "NODE_NAME" } "" } } { "prog_ram.v" "" { Text "C:/altera/lab5/prog_ram.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(2.687 ns) 9.289 ns instruction\[1\] 5 PIN PIN_C13 0 " "Info: 5: + IC(1.828 ns) + CELL(2.687 ns) = 9.289 ns; Loc. = PIN_C13; Fanout = 0; PIN Node = 'instruction\[1\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "4.515 ns" { prog_ram:prog_ram|instruction[1] instruction[1] } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.901 ns 74.29 % " "Info: Total cell delay = 6.901 ns ( 74.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.388 ns 25.71 % " "Info: Total interconnect delay = 2.388 ns ( 25.71 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "9.289 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[1] instruction[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "9.289 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[1] instruction[1] } { 0.000ns 0.426ns 0.134ns 0.000ns 1.828ns } { 0.000ns 0.366ns 0.075ns 3.773ns 2.687ns } } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.819 ns" { clock cpu:cpu|ram_addr[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.819 ns" { clock clock~out0 cpu:cpu|ram_addr[3] } { 0.000ns 0.000ns 1.552ns } { 0.000ns 0.725ns 0.542ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "9.289 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[1] instruction[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "9.289 ns" { cpu:cpu|ram_addr[3] prog_ram:prog_ram|reduce_or~408 prog_ram:prog_ram|reduce_or~409 prog_ram:prog_ram|instruction[1] instruction[1] } { 0.000ns 0.426ns 0.134ns 0.000ns 1.828ns } { 0.000ns 0.366ns 0.075ns 3.773ns 2.687ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "memory:memory\|data_out\[0\] rst clock -0.953 ns register " "Info: th for register \"memory:memory\|data_out\[0\]\" (data pin = \"rst\", clock pin = \"clock\") is -0.953 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.800 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 62 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 62; CLK Node = 'clock'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { clock } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.533 ns) + CELL(0.542 ns) 2.800 ns memory:memory\|data_out\[0\] 2 REG LC_X29_Y26_N3 1 " "Info: 2: + IC(1.533 ns) + CELL(0.542 ns) = 2.800 ns; Loc. = LC_X29_Y26_N3; Fanout = 1; REG Node = 'memory:memory\|data_out\[0\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.075 ns" { clock memory:memory|data_out[0] } "NODE_NAME" } "" } } { "memory.v" "" { Text "C:/altera/lab5/memory.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.25 % " "Info: Total cell delay = 1.267 ns ( 45.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns 54.75 % " "Info: Total interconnect delay = 1.533 ns ( 54.75 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.800 ns" { clock memory:memory|data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.800 ns" { clock clock~out0 memory:memory|data_out[0] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.725ns 0.542ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "memory.v" "" { Text "C:/altera/lab5/memory.v" 3 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.853 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns rst 1 PIN PIN_L3 29 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 29; PIN Node = 'rst'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "" { rst } "NODE_NAME" } "" } } { "lab2_sim.v" "" { Text "C:/altera/lab5/lab2_sim.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.075 ns) 2.808 ns memory:memory\|data_out\[0\]~43 2 COMB LC_X29_Y26_N2 4 " "Info: 2: + IC(1.905 ns) + CELL(0.075 ns) = 2.808 ns; Loc. = LC_X29_Y26_N2; Fanout = 4; COMB Node = 'memory:memory\|data_out\[0\]~43'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.980 ns" { rst memory:memory|data_out[0]~43 } "NODE_NAME" } "" } } { "memory.v" "" { Text "C:/altera/lab5/memory.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.705 ns) 3.853 ns memory:memory\|data_out\[0\] 3 REG LC_X29_Y26_N3 1 " "Info: 3: + IC(0.340 ns) + CELL(0.705 ns) = 3.853 ns; Loc. = LC_X29_Y26_N3; Fanout = 1; REG Node = 'memory:memory\|data_out\[0\]'" { } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "1.045 ns" { memory:memory|data_out[0]~43 memory:memory|data_out[0] } "NODE_NAME" } "" } } { "memory.v" "" { Text "C:/altera/lab5/memory.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns 41.73 % " "Info: Total cell delay = 1.608 ns ( 41.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.245 ns 58.27 % " "Info: Total interconnect delay = 2.245 ns ( 58.27 % )" { } { } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "3.853 ns" { rst memory:memory|data_out[0]~43 memory:memory|data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "3.853 ns" { rst rst~out0 memory:memory|data_out[0]~43 memory:memory|data_out[0] } { 0.000ns 0.000ns 1.905ns 0.340ns } { 0.000ns 0.828ns 0.075ns 0.705ns } } } } 0} } { { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "2.800 ns" { clock memory:memory|data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "2.800 ns" { clock clock~out0 memory:memory|data_out[0] } { 0.000ns 0.000ns 1.533ns } { 0.000ns 0.725ns 0.542ns } } } { "C:/altera/lab5/db/lab5_cmp.qrpt" "" { Report "C:/altera/lab5/db/lab5_cmp.qrpt" Compiler "lab5" "UNKNOWN" "V1" "C:/altera/lab5/db/lab5.quartus_db" { Floorplan "C:/altera/lab5/" "" "3.853 ns" { rst memory:memory|data_out[0]~43 memory:memory|data_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50sp1/bin/Technology_Viewer.qrui" "3.853 ns" { rst rst~out0 memory:memory|data_out[0]~43 memory:memory|data_out[0] } { 0.000ns 0.000ns 1.905ns 0.340ns } { 0.000ns 0.828ns 0.075ns 0.705ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 01:19:42 2007 " "Info: Processing ended: Wed Oct 10 01:19:42 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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